Issued Patents All Time
Showing 25 most recent of 39 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12314193 | Scheduling of read operations and write operations based on a data bus mode | Wei Wang, Jiangli Zhu, Ying Yu Tai | 2025-05-27 |
| 12135876 | Memory systems having controllers embedded in packages of integrated circuit memory | Gurpreet Anand, Ying Yu Tai, Cheng Yuan Wu | 2024-11-05 |
| 12061544 | CPU cache flushing to persistent memory | Paul Stonelake | 2024-08-13 |
| 12019780 | Memory device data security based on content-addressable memory architecture | Tomoko Ogura Iwasaki, Manik Advani | 2024-06-25 |
| 11977787 | Remote direct memory access in multi-tier memory systems | Parag R. Maharana, Anirban Ray, Gurpreet Anand | 2024-05-07 |
| 11874779 | Scheduling of read operations and write operations based on a data bus mode | Wei Wang, Jiangli Zhu, Ying Yu Tai | 2024-01-16 |
| 11869618 | Memory sub-system including an in-package sequencer to perform error correction and memory testing operations | Ying Yu Tai, Cheng Yuan Wu, Jiangli Zhu | 2024-01-09 |
| 11836380 | NVMe direct virtualization with configurable storage | Parag R. Maharana, Anirban Ray, Gurpreet Anand, Samir Rajadnya, Paul Stonelake | 2023-12-05 |
| 11675714 | Memory sub-system including an in package sequencer separate from a controller | Ying Yu Tai, Cheng Yuan Wu | 2023-06-13 |
| 11669260 | Predictive data orchestration in multi-tier memory systems | Anirban Ray, Gurpreet Anand | 2023-06-06 |
| 11663133 | Memory tiering using PCIe connected far memory | Anirban Ray, Paul Stonelake, Gurpreet Anand | 2023-05-30 |
| 11630594 | Storing data based on a probability of a data graph | Anirban Ray, Gurpreet Anand | 2023-04-18 |
| 11573901 | Predictive paging to accelerate memory access | Anirban Ray, Gurpreet Anand, Parag R. Maharana | 2023-02-07 |
| 11568077 | Memory device data security based on content-addressable memory architecture | Tomoko Ogura Iwasaki, Manik Advani | 2023-01-31 |
| 11567817 | Providing bandwidth expansion for a memory sub-system including a sequencer separate from a controller | Ying Yu Tai, Cheng Yuan Wu | 2023-01-31 |
| 11561845 | Memory access communications through message passing interface implemented in memory systems | Gurpreet Anand, Anirban Ray, Parag R. Maharana | 2023-01-24 |
| 11561902 | Cache operations in a hybrid dual in-line memory module | Paul Stonelake, Horia Simionescu, Robert W. Walker, Anirban Ray, Gurpreet Anand | 2023-01-24 |
| 11404092 | Cross point array memory in a non-volatile dual in-line memory module | Edward C. McGlaughlin, Ying Yu Tai | 2022-08-02 |
| 11379373 | Memory tiering using PCIe connected far memory | Anirban Ray, Paul Stonelake, Gurpreet Anand | 2022-07-05 |
| 11354056 | Predictive data orchestration in multi-tier memory systems | Anirban Ray, Gurpreet Anand | 2022-06-07 |
| 11169920 | Cache operations in a hybrid dual in-line memory module | Paul Stonelake, Horia Simionescu, Robert M. Walker, Anirban Ray, Gurpreet Anand | 2021-11-09 |
| 11119679 | Storing data based on a probability of a data graph | Anirban Ray, Gurpreet Anand | 2021-09-14 |
| 11099789 | Remote direct memory access in multi-tier memory systems | Parag R. Maharana, Anirban Ray, Gurpreet Anand | 2021-08-24 |
| 11080210 | Memory sub-system including an in package sequencer separate from a controller | Ying Yu Tai, Cheng Yuan Wu | 2021-08-03 |
| 11068203 | NVMe direct virtualization with configurable storage | Parag R. Maharana, Anirban Ray, Gurpreet Anand, Samir Rajadnya, Paul Stonelake | 2021-07-20 |