Issued Patents All Time
Showing 1–25 of 139 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12423227 | Generating virtual blocks using partial good blocks | Zhongguang Xu, Guang Hu, Xiangang Luo, Ting Luo, Zhenming Zhou +1 more | 2025-09-23 |
| 12417035 | Modified read counter incrementing scheme in a memory sub-system | Kishore Kumar Muchherla, Jonathan S. Parry, Nicola Ciocchini, Animesh Chowdhury, Akira Goda +2 more | 2025-09-16 |
| 12299304 | Automatic wordline status bypass management | Jiangang Wu, Qisong Lin, Kishore Kumar Muchherla | 2025-05-13 |
| 12271592 | Independent plane architecture in a memory device | Andrea Giovanni Xotta, Dheeraj Srinivasan, Ali Mohammadzadeh, Karl D. Schuh, Guido Luciano Rizzo +7 more | 2025-04-08 |
| 12216915 | Adaptive read disturb scan | Animesh Chowdhury, Kishore Kumar Muchherla, Nicola Ciocchini, Akira Goda, Niccolo′ Righetti +1 more | 2025-02-04 |
| 12182407 | Monitoring flash memory erase progress using erase credits | Giuseppe Cariello, Fulvio Rori | 2024-12-31 |
| 12142343 | Memory devices for multiple read operations | Eric N. Lee, Kishore Kumar Muchherla, Jeffrey S. McNeil | 2024-11-12 |
| 12131788 | Read counter adjustment for delaying read disturb scans | Nicola Ciocchini, Animesh Chowdhury, Kishore Kumar Muchherla, Akira Goda, Niccolo' Righetti +1 more | 2024-10-29 |
| 12067290 | On-die cross-temperature management for a memory device | Kishore Kumar Muchherla, Violante Moschiano, Akira Goda, Jeffrey S. McNeil, Sivagnanam Parthasarathy +2 more | 2024-08-20 |
| 12026385 | Automatic wordline status bypass management | Jiangang Wu, Qisong Lin, Kishore Kumar Muchherla | 2024-07-02 |
| 12001340 | Full multi-plane operation enablement | Jiangang Wu, Qisong Lin, Yunqiu Wan, Ashutosh Malshe, Peng-Cheng Chen | 2024-06-04 |
| 11922029 | Modified read counter incrementing scheme in a memory sub-system | Kishore Kumar Muchherla, Jonathan S. Parry, Nicola Ciocchini, Animesh Chowdhury, Akira Goda +2 more | 2024-03-05 |
| 11915785 | Memory sub-system management based on dynamic control of wordline start voltage | Jiangang Wu, Lei Zhou, Kishore Kumar Muchherla, Qisong Lin | 2024-02-27 |
| 11847065 | Memory sub-system management of firmware block record and device block record | Jiangang Wu, Qisong Lin, Mark Ish, Peng Xu | 2023-12-19 |
| 11803321 | Interruption of program operations at a memory sub-system | Horia Simionescu, Rohitkumar Makhija, Peng-Cheng Chen | 2023-10-31 |
| 11797383 | Redundant array of independent NAND for a three-dimensional memory array | Sampath K. Ratnam, Renato C. Padilla, Kishore Kumar Muchherla, Sivagnanam Parthasarathy, Peter Feeley | 2023-10-24 |
| 11776655 | Memory device virtual blocks using half good blocks | Sri Rama Namala, Jianmin Huang, Ashutosh Malshe, Xiangang Luo | 2023-10-03 |
| 11756594 | Memory devices for multiple read operations | Eric N. Lee, Kishore Kumar Muchherla, Jeffrey S. McNeil | 2023-09-12 |
| 11710533 | NAND flash array defect real time detection | Xiaojiang Guo, Michele Piccardi, Manan Tripathi | 2023-07-25 |
| 11698864 | Memory access collision management on a shared wordline | AbdelHakim S. Alhussien, Jiangang Wu, Karl D. Schuh, Qisong Lin | 2023-07-11 |
| 11693774 | Selectively utilizing a read page cache mode in a memory subsystem | Jiangang Wu, Jing Liu, Kishore Kumar Muchherla, Mark Ish, Myoung Jun Go +2 more | 2023-07-04 |
| 11688473 | SLC page read | Harish Reddy Singidi, Scott Anthony Stoller, Ashutosh Malshe, Gianni Stephen Alsasua, Kishore Kumar Muchherla | 2023-06-27 |
| 11682462 | Charge loss compensation | Kalyan C. Kavalipurapu | 2023-06-20 |
| 11615029 | Full multi-plane operation enablement | Jiangang Wu, Qisong Lin, Yunqiu Wan, Ashutosh Malshe, Peng-Cheng Chen | 2023-03-28 |
| 11610632 | NAND temperature data management | Kishore Kumar Muchherla, Sampath K. Ratnam, Preston A. Thomson, Harish Reddy Singidi, Peter Feeley +1 more | 2023-03-21 |