Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
PF

Peter Feeley — 205 Patents

Micron: 203 patents #38 of 6,374Top 1%
AAAdvanced Hardware Architecture: 2 patents #4 of 10Top 40%
Boise, ID: #16 of 3,546 inventorsTop 1%
Idaho: #26 of 8,810 inventorsTop 1%
Overall (All Time): #3,200 of 4,157,543Top 1%
205 Patents All Time
Peter Feeley has been granted 205 US patents while listed as an inventor at Micron. The first was granted in 1996 and the most recent in December 2025. Peter Feeley ranks #3,200 of 4,157,543 US inventors in our database (top 0.08%). Patent records list Peter Feeley in Boise, ID, US.

Issued Patents All Time

Showing 1–25 of 205 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12511232 Trim setting determination on a memory device Aswin Thiruvengadam, Daniel L. Lowrance 2025-12-30
12498886 Buffer allocation for reducing block transit penalty Kishore Kumar Muchherla, Jingde Zhu, Faliang Zhu, Akira Goda, Lakshmi Kalpana Vakati +3 more 2025-12-16
12481463 Multiple-pass programming of memory cells using temporary parity generation Kishore Kumar Muchherla, Lakshmi Kalpana Vakati, Dave Scott Ebsen, Sanjay Subbarao, Vivek Shivhare +3 more 2025-11-25
12430243 Using a common pool of blocks for user data and a system data structure Kishore Kumar Muchherla, Kulachet Tanpairoj, Sampath K. Ratnam, Ashutosh Malshe 2025-09-30
12393363 Voltage bin calibration based on a voltage distribution reference voltage Kishore Kumar Muchherla, Devin M. Batutis, Xiangang Luo, Mustafa N. Kaynak, Sivagnanam Parthasarathy +2 more 2025-08-19
12367942 Trim setting determination for a memory device Aswin Thiruvengadam, Daniel L. Lowrance 2025-07-22
12307111 Block family-based error avoidance for memory devices Michael Sheperek, Kishore Kumar Muchherla, Mustafa N. Kaynak, Vamsi Pavan Rayaprolu, Bruce A. Liikanen +3 more 2025-05-20
12229000 Managing error-handling flows in memory devices Kishore Kumar Muchherla, Shane Nowell, Mustafa N. Kaynak, Sampath K. Ratnam, Sivagnanam Parthasarathy +2 more 2025-02-18
12216573 Memory device with dynamic cache management Kishore Kumar Muchherla, Ashutosh Malshe, Daniel J. Hubbard, Christopher S. Hale, Kevin R. Brandt +3 more 2025-02-04
12131020 Memory devices and systems including static and dynamic caches, and related methods Kishore Kumar Muchherla, Ashutosh Malshe, Sampath K. Ratnam, Michael G. Miller, Christopher S. Hale +1 more 2024-10-29 $30,986,000
12079517 Buffer allocation for reducing block transit penalty Kishore Kumar Muchherla, Jiangli Zhu, Fangfang Zhu, Akira Goda, Lakshmi Kalpana Vakati +3 more 2024-09-03 $19,072,000
12057185 Voltage calibration scans to reduce memory device overhead Kishore Kumar Muchherla, Mustafa N. Kaynak, Sivagnanam Parthasarathy, Xiangang Luo, Devin M. Batutis +4 more 2024-08-06 $38,187,000
12051479 Memory block programming using defectivity information Kishore Kumar Muchherla, Akira Goda, Dave Scott Ebsen, Lakshmi Kalpana Vakati, Jiangli Zhu +3 more 2024-07-30 $28,317,000
12001721 Multiple-pass programming of memory cells using temporary parity generation Kishore Kumar Muchherla, Lakshmi Kalpana Vakati, Dave Scott Ebsen, Sanjay Subbarao, Vivek Shivhare +3 more 2024-06-04 $27,497,000
11966616 Voltage bin calibration based on a voltage distribution reference voltage Kishore Kumar Muchherla, Devin M. Batutis, Xiangang Luo, Mustafa N. Kaynak, Sivagnanam Parthasarathy +2 more 2024-04-23 $30,870,000
11928347 Managing voltage bin selection for blocks of a memory device Kishore Kumar Muchherla, Mustafa N. Kaynak, Sampath K. Ratnam, Shane Nowell, Sivagnanam Parthasarathy +2 more 2024-03-12 $21,460,000
11899966 Implementing fault tolerant page stripes on low density memory systems Kishore Kumar Muchherla, Mark A. Helm, Giuseppina Puzzilli, Yifen Liu, Violante Moschiano +2 more 2024-02-13 $12,832,000
11886726 Block family-based error avoidance for memory devices Michael Sheperek, Kishore Kumar Muchherla, Mustafa N. Kaynak, Vamsi Pavan Rayaprolu, Bruce A. Liikanen +3 more 2024-01-30 $12,191,000
11869605 Adjusting pass-through voltage based on threshold voltage shift Kishore Kumar Muchherla, Mustafa N. Kaynak, Sampath K. Ratnam, Sivagnanam Parthasarathy 2024-01-09 $10,439,000
11868639 Providing recovered data to a new memory cell at a memory sub-system based on an unsuccessful error correction operation Sampath K. Ratnam, Vamsi Pavan Rayaprolu, Mustafa N. Kaynak, Sivagnanam Parthasarathy, Kishore Kumar Muchherla +2 more 2024-01-09 $10,439,000
11853205 Memory device with dynamic cache management Kishore Kumar Muchherla, Ashutosh Malshe, Daniel J. Hubbard, Christopher S. Hale, Kevin R. Brandt +3 more 2023-12-26 $15,560,000
11854634 Selectable trim settings on a memory device Aswin Thiruvengadam, Daniel L. Lowrance 2023-12-26 $15,560,000
11853207 Configurable trim settings on a memory device Aswin Thiruvengadam, Daniel L. Lowrance 2023-12-26 $15,560,000
11837307 Managing error-handling flows in memory devices Kishore Kumar Muchherla, Shane Nowell, Mustafa N. Kaynak, Sampath K. Ratnam, Sivagnanam Parthasarathy +2 more 2023-12-05 $17,549,000
11836078 Trim setting determination on a memory device Aswin Thiruvengadam, Daniel L. Lowrance 2023-12-05 $17,549,000