Issued Patents All Time
Showing 25 most recent of 57 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12216541 | Block failure protection for zone memory system | — | 2025-02-04 |
| 12130748 | Caching of logical-to-physical mapping information in a memory sub-system | — | 2024-10-29 |
| 12124380 | Storing a logical-to-physical mapping in NAND memory | — | 2024-10-22 |
| 12079517 | Buffer allocation for reducing block transit penalty | Kishore Kumar Muchherla, Peter Feeley, Jiangli Zhu, Fangfang Zhu, Akira Goda +3 more | 2024-09-03 |
| 12051479 | Memory block programming using defectivity information | Kishore Kumar Muchherla, Akira Goda, Dave Scott Ebsen, Lakshmi Kalpana Vakati, Jiangli Zhu +3 more | 2024-07-30 |
| 12050809 | Multi-pass data programming in a memory sub-system having multiple dies and planes | Steven S. Williams, Mark Ish, John E. Maroney | 2024-07-30 |
| 12045168 | Timed data transfer between a host system and a memory sub-system | — | 2024-07-23 |
| 12001721 | Multiple-pass programming of memory cells using temporary parity generation | Kishore Kumar Muchherla, Lakshmi Kalpana Vakati, Dave Scott Ebsen, Peter Feeley, Vivek Shivhare +3 more | 2024-06-04 |
| 11922011 | Virtual management unit scheme for two-pass programming in a memory sub-system | Johnny A. Lam, Samyukta Mudugal, Byron D. Harris, Daniel A. Boals | 2024-03-05 |
| 11914471 | Block failure protection for zone memory system | — | 2024-02-27 |
| 11868287 | Just-in-time (JIT) scheduler for memory subsystems | Johnny A. Lam, Alex J. Wesenberg, Guanying Wu, Chandra M. Guda | 2024-01-09 |
| 11782643 | Partial execution of a write command from a host system | Mark Ish | 2023-10-10 |
| 11782841 | Management of programming mode transitions to accommodate a constant size of data transfer between a host system and a memory sub-system | James Fitzpatrick | 2023-10-10 |
| 11755495 | Storing a logical-to-physical mapping in NAND memory | — | 2023-09-12 |
| 11734189 | Caching of logical-to-physical mapping information in a memory sub-system | — | 2023-08-22 |
| 11726703 | Extending size of memory unit | — | 2023-08-15 |
| 11714562 | Journal scheme for two-pass programming memory devices | Johnny A. Lam, Samyukta Mudugal | 2023-08-01 |
| 11709632 | Input/output size control between a host system and a memory sub-system | Mark Ish | 2023-07-25 |
| 11676679 | Two-layer code with low parity cost for memory sub-systems | James Fitzpatrick | 2023-06-13 |
| 11669272 | Predictive data transfer based on availability of media units in memory sub-systems | Steven S. Williams, Mark Ish | 2023-06-06 |
| 11640354 | Logical-to-physical mapping of data groups with data locality | Johnny A. Lam, John E. Maroney, Mark Ish | 2023-05-02 |
| 11573742 | Dynamic data placement for collision avoidance among concurrent write streams | — | 2023-02-07 |
| 11487666 | Timed data transfer between a host system and a memory sub-system | — | 2022-11-01 |
| 11409461 | Extending size of memory unit | — | 2022-08-09 |
| 11294820 | Management of programming mode transitions to accommodate a constant size of data transfer between a host system and a memory sub-system | James Fitzpatrick | 2022-04-05 |