Issued Patents All Time
Showing 1–25 of 77 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12393510 | Namespace management for memory sub-systems | Alexei Frolikov | 2025-08-19 |
| 12230332 | Suspending memory erase operations to perform higher priority memory commands | Shakeel Isamohiuddin Bukhari | 2025-02-18 |
| 12182447 | Dynamic selection of cores for processing responses | Yun Li, Scheheresade Virani, John Paul Traver, Ning Zhao | 2024-12-31 |
| 12079065 | Caching lookup tables for block family error avoidance | Shakeel Isamohiuddin Bukhari | 2024-09-03 |
| 12050809 | Multi-pass data programming in a memory sub-system having multiple dies and planes | Sanjay Subbarao, Steven S. Williams, John E. Maroney | 2024-07-30 |
| 12050776 | Apparatus with response completion pacing | Ying Huang | 2024-07-30 |
| 11966635 | Logical unit number queues and logical unit number queue scheduling for memory devices | Shakeel Isamohiuddin Bukhari | 2024-04-23 |
| 11960740 | Implementing automatic rate control in a memory sub-system | Ying Huang | 2024-04-16 |
| 11847065 | Memory sub-system management of firmware block record and device block record | Jiangang Wu, Jung Sheng Hoei, Qisong Lin, Peng Xu | 2023-12-19 |
| 11782643 | Partial execution of a write command from a host system | Sanjay Subbarao | 2023-10-10 |
| 11720681 | Firmware execution profiling and verification | Yun Li, Harini Komandur Elayavalli | 2023-08-08 |
| 11720289 | Block family tracking for memory devices | — | 2023-08-08 |
| 11709632 | Input/output size control between a host system and a memory sub-system | Sanjay Subbarao | 2023-07-25 |
| 11709732 | Mitigating read disturb effects in memory devices | Gerald L. Cadloni, James P. Crowley | 2023-07-25 |
| 11693774 | Selectively utilizing a read page cache mode in a memory subsystem | Jiangang Wu, Jing Liu, Jung Sheng Hoei, Kishore Kumar Muchherla, Myoung Jun Go +2 more | 2023-07-04 |
| 11675695 | Namespace management for memory sub-systems | Alexei Frolikov | 2023-06-13 |
| 11669272 | Predictive data transfer based on availability of media units in memory sub-systems | Sanjay Subbarao, Steven S. Williams | 2023-06-06 |
| 11640354 | Logical-to-physical mapping of data groups with data locality | Sanjay Subbarao, Johnny A. Lam, John E. Maroney | 2023-05-02 |
| 11630779 | Hybrid storage device with three-level memory mapping | Nitin Satishchandra Kabra, Jackson L. Ellis, Niranjan Anant Pol | 2023-04-18 |
| 11579799 | Dynamic selection of cores for processing responses | Yun Li, Scheheresade Virani, John Paul Traver, Ning Zhao | 2023-02-14 |
| 11556258 | Implementing automatic rate control in a memory sub-system | Ying Huang | 2023-01-17 |
| 11513959 | Managing collisions in a non-volatile memory system with a coherency checker | Horia Simionescu, Lyle E. Adams, Yongcai Xu | 2022-11-29 |
| 11481348 | Handling operation collisions in a non-volatile memory | Lyle E. Adams, Pushpa Seetamraju, Karl D. Schuh, Dan Tupy | 2022-10-25 |
| 11449431 | Data storage device with rewritable in-place memory | Timothy Canepa, David Scott Ebsen | 2022-09-20 |
| 11379304 | Mitigating read disturb effects in memory devices | Gerald L. Cadloni, James P. Crowley | 2022-07-05 |