Issued Patents All Time
Showing 25 most recent of 40 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12314582 | Performance control for a memory sub-system | James P. Crowley, Jiangang Wu, Peng Xu | 2025-05-27 |
| 12229452 | Read counter for quality of service design | Jiangang Wu, James P. Crowley | 2025-02-18 |
| 12216573 | Memory device with dynamic cache management | Kishore Kumar Muchherla, Peter Feeley, Ashutosh Malshe, Daniel J. Hubbard, Christopher S. Hale +3 more | 2025-02-04 |
| 12182447 | Dynamic selection of cores for processing responses | Mark Ish, Scheheresade Virani, John Paul Traver, Ning Zhao | 2024-12-31 |
| 12115967 | Power control device and power control method | Chih-Chiang Wu, Uma Sankar ROUT, Bang-Yuan Liu | 2024-10-15 |
| 11956307 | Distributed task offloading and computing resources management method based on energy harvesting | Zhixiu Yao, Shichao XIA, Guangfu Wu | 2024-04-09 |
| 11899948 | Performance control for a memory sub-system | James P. Crowley, Jiangang Wu, Peng Xu | 2024-02-13 |
| 11853205 | Memory device with dynamic cache management | Kishore Kumar Muchherla, Peter Feeley, Ashutosh Malshe, Daniel J. Hubbard, Christopher S. Hale +3 more | 2023-12-26 |
| 11831708 | Distributed computation offloading method based on computation-network collaboration in stochastic network | Shichao XIA, Zhixiu Yao, Guangfu Wu, Hongcheng Zhuang, Zhaocheng Wang | 2023-11-28 |
| 11765634 | Evolutionary game-based multi-user switching method in software-defined satellite network system | Guangfu Wu, Mengmeng Liu | 2023-09-19 |
| 11756626 | Memory die resource management | Jiangang Wu, James P. Crowley | 2023-09-12 |
| 11755227 | Command batching for a memory sub-system | John Paul Traver, Scheheresade Virani, Ning Zhao, Tom V. Geukens | 2023-09-12 |
| 11726669 | Coherency locking schemes | John Paul Traver | 2023-08-15 |
| 11726716 | Internal commands for access operations | John Paul Traver, Ning Zhao, Tom V. Geukens | 2023-08-15 |
| 11720681 | Firmware execution profiling and verification | Harini Komandur Elayavalli, Mark Ish | 2023-08-08 |
| 11720493 | Cache management based on memory device over-provisioning | Kevin R. Brandt, Peter Feeley, Kishore Kumar Muchherla, Sampath K. Ratnam, Ashutosh Malshe +2 more | 2023-08-08 |
| 11693768 | Power loss data protection in a memory sub-system | Peng Xu, Jiangang Wu | 2023-07-04 |
| 11675701 | Hardware-based coherency checking techniques | — | 2023-06-13 |
| 11593261 | Memory device with dynamic cache management | Kishore Kumar Muchherla, Peter Feeley, Ashutosh Malshe, Daniel J. Hubbard, Christopher S. Hale +3 more | 2023-02-28 |
| 11579799 | Dynamic selection of cores for processing responses | Mark Ish, Scheheresade Virani, John Paul Traver, Ning Zhao | 2023-02-14 |
| 11544188 | Memory device with dynamic storage mode control | Kishore Kumar Muchherla, Peter Feeley, Ashutosh Malshe, Daniel J. Hubbard, Christopher S. Hale +2 more | 2023-01-03 |
| 11520502 | Performance control for a memory sub-system | James P. Crowley, Jiangang Wu, Peng Xu | 2022-12-06 |
| 11385820 | Command batching for a memory sub-system | John Paul Traver, Scheheresade Virani, Ning Zhao, Tom V. Geukens | 2022-07-12 |
| 11374515 | Operation method and operation device of motor driver for driving motor | Chih-Chiang Wu, Hsin-Ping Chou, Shih Hsiang Wu | 2022-06-28 |
| 11287987 | Coherency locking schemes | John Paul Traver | 2022-03-29 |