Issued Patents All Time
Showing 25 most recent of 66 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12299326 | Adaptive command completion timers | Daniel J. Hubbard | 2025-05-13 |
| 12299318 | Data reordering at a memory subsystem | Kishore Kumar Muchherla, Daniel J. Hubbard, James Fitzpatrick | 2025-05-13 |
| 12271592 | Independent plane architecture in a memory device | Andrea Giovanni Xotta, Dheeraj Srinivasan, Ali Mohammadzadeh, Guido Luciano Rizzo, Jung Sheng Hoei +7 more | 2025-04-08 |
| 12182013 | Memory sub-system write sequence track | Vamsi Pavan Rayaprolu, Jiangang Wu, Kishore Kumar Muchherla | 2024-12-31 |
| 12164804 | Memory sub-system media management groups | Jiangang Wu, Kishore Kumar Muchherla, Ashutosh Malshe, Vamsi Pavan Rayaprolu | 2024-12-10 |
| 12148484 | Memory sub-system scan | Vamsi Pavan Rayaprolu, Jeffrey S. McNeil, Kishore Kumar Muchherla, Ashutosh Malshe, Jiangang Wu | 2024-11-19 |
| 12073873 | Dynamic buffer limit for at-risk data | William Akin | 2024-08-27 |
| 12067253 | Opportunistic background data integrity scans | William Akin | 2024-08-20 |
| 12057185 | Voltage calibration scans to reduce memory device overhead | Kishore Kumar Muchherla, Mustafa N. Kaynak, Sivagnanam Parthasarathy, Xiangang Luo, Peter Feeley +4 more | 2024-08-06 |
| 11995326 | Selective partitioning of sets of pages programmed to memory device | Kishore Kumar Muchherla, Jiangang Wu, Mastafa N. Kaynak, Devin M. Batutis, Xiangang Luo | 2024-05-28 |
| 11934686 | Data reordering at a memory subsystem | Kishore Kumar Muchherla, Daniel J. Hubbard, James Fitzpatrick | 2024-03-19 |
| 11928347 | Managing voltage bin selection for blocks of a memory device | Kishore Kumar Muchherla, Mustafa N. Kaynak, Peter Feeley, Sampath K. Ratnam, Shane Nowell +2 more | 2024-03-12 |
| 11886336 | Managing workload of programming sets of pages to memory device | Kishore Kumar Muchherla, Jiangang Wu, Mustafa N. Kaynak, Devin M. Batutis, Xiangang Luo | 2024-01-30 |
| 11861228 | Memory status command aggregation | Ali Mohammadzadeh, Dheeraj Srinivasan, Daniel J. Hubbard, Luca Bert | 2024-01-02 |
| 11847051 | Memory sub-system logical block address remapping | Kishore Kumar Muchherla, Vamsi Pavan Rayaprolu, Jiangang Wu, Gil Golov | 2023-12-19 |
| 11841794 | Memory sub-system write sequence track | Vamsi Pavan Rayaprolu, Jiangang Wu, Kishore Kumar Muchherla | 2023-12-12 |
| 11836377 | Data transfer management within a memory device having multiple memory regions with different memory densities | AbdelHakim S. Alhussien, Ayberk Ozturk, Luca Bert | 2023-12-05 |
| 11823748 | Voltage bin calibration based on a temporary voltage shift offset | Kishore Kumar Muchherla, Mustafa N. Kaynak, Xiangang Luo, Shane Nowell, Devin M. Batutis +4 more | 2023-11-21 |
| 11797216 | Read calibration based on ranges of program/erase cycles | Vamsi Pavan Rayaprolu, Giuseppina Puzzilli, Jeffrey S. McNeil, Kishore Kumar Muchherla, Ashutosh Malshe +1 more | 2023-10-24 |
| 11797435 | Zone based reconstruction of logical to physical address translation map | Daniel A. Boals, Byron D. Harris, Amy Lee Wohlschlegel | 2023-10-24 |
| 11783901 | Multi-tier threshold voltage offset bin calibration | Kishore Kumar Muchherla, Shane Nowell, Mustafa N. Kaynak, Jiangang Wu, Devin M. Batutis +1 more | 2023-10-10 |
| 11748013 | Grouping blocks based on power cycle and power on time | Kishore Kumar Muchherla, Mustafa N. Kaynak, Jiangang Wu, Sampath K. Ratnam, Sivagnanam Parthasarathy +1 more | 2023-09-05 |
| 11698864 | Memory access collision management on a shared wordline | AbdelHakim S. Alhussien, Jiangang Wu, Qisong Lin, Jung Sheng Hoei | 2023-07-11 |
| 11688479 | Read window based on program/erase cycles | Vamsi Pavan Rayaprolu, Giuseppina Puzzilli, Jeffrey S. McNeil, Kishore Kumar Muchherla, Ashutosh Malshe +1 more | 2023-06-27 |
| 11676664 | Voltage bin selection for blocks of a memory device after power up of the memory device | Kishore Kumar Muchherla, Sampath K. Ratnam, Shane Nowell, Sivagnanam Parthasarathy, Mustafa N. Kaynak +2 more | 2023-06-13 |