Issued Patents All Time
Showing 1–25 of 154 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12412632 | Managing compensation for charge coupling and lateral migration in memory devices | Patrick R. Khayat, Sivagnanam Parthasarathy | 2025-09-09 |
| 12393363 | Voltage bin calibration based on a voltage distribution reference voltage | Kishore Kumar Muchherla, Devin M. Batutis, Xiangang Luo, Peter Feeley, Sivagnanam Parthasarathy +2 more | 2025-08-19 |
| 12354670 | Dynamic adjustment of offset voltages for reading memory cells in a memory device | Sivagnanam Parthasarathy, Patrick R. Khayat | 2025-07-08 |
| 12348244 | Detecting a stall condition in bit flipping decoding using syndrome weight slope | Sivagnanam Parthasarathy | 2025-07-01 |
| 12332742 | Memory compaction management in memory devices | Vamsi Pavan Rayaprolu, Sivagnanam Parthasarathy, Patrick R. Khayat, Sampath K. Ratnam, Kishore Kumar Muchherla +2 more | 2025-06-17 |
| 12332743 | Efficient memory use to support soft information in bit flipping decoders | Eyal En Gad, Zhengang Chen, Sivagnanam Parthasarathy, Phong Sy Nguyen, Dung Viet Nguyen | 2025-06-17 |
| 12328129 | Bypassing iterations in a bit flipping decoder using a least reliable bit energy function | Eyal En Gad, Sivagnanam Parthasarathy | 2025-06-10 |
| 12326782 | Adjustment of code rate as function of memory endurance state metric | Kishore Kumar Muchherla, Niccolo' Righetti, Sivagnanam Parthasarathy, Mark A. Helm, James Fitzpatrick +1 more | 2025-06-10 |
| 12321613 | Bit flipping decoder with optimized maximum iterations for varied bit flipping thresholds | Eyal En Gad, Sivagnanam Parthasarathy | 2025-06-03 |
| 12307111 | Block family-based error avoidance for memory devices | Michael Sheperek, Kishore Kumar Muchherla, Vamsi Pavan Rayaprolu, Bruce A. Liikanen, Peter Feeley +3 more | 2025-05-20 |
| 12301254 | Early stopping of bit-flip low density parity check decoding based on syndrome weight | Eyal En Gad, Yoav Weinberg, Zhengang Chen, Sivagnanam Parthasarathy | 2025-05-13 |
| 12266420 | Temperature-compensated time estimate for a block to reach a uniform charge loss state | Patrick R. Khayat, Steven Michael Kientz, Sivagnanam Parthasarathy, Vamsi Pavan Rayaprolu | 2025-04-01 |
| 12229000 | Managing error-handling flows in memory devices | Kishore Kumar Muchherla, Shane Nowell, Sampath K. Ratnam, Peter Feeley, Sivagnanam Parthasarathy +2 more | 2025-02-18 |
| 12223190 | Measurement of representative charge loss in a block to determine charge loss state | Patrick R. Khayat, Steven Michael Kientz, Sivagnanam Parthasarathy, Vamsi Pavan Rayaprolu | 2025-02-11 |
| 12197742 | Managing error compensation using charge coupling and lateral migration sensitivity | Patrick R. Khayat, Sivagnanam Parthasarathy | 2025-01-14 |
| 12142333 | Error correction in a memory device having an error correction code of a predetermined code rate | Kishore Kumar Muchherla | 2024-11-12 |
| 12119062 | Managing compensation for cell-to-cell coupling and lateral migration in memory devices based on a sensitivity metric | Patrick R. Khayat, Sivagnanam Parthasarathy | 2024-10-15 |
| 12099725 | Code rate as function of logical saturation | Kishore Kumar Muchherla, Jonathan S. Parry, Sivagnanam Parthasarathy, Akira Goda | 2024-09-24 |
| 12087374 | Managing compensation for cell-to-cell coupling and lateral migration in memory devices using segmentation | Patrick R. Khayat, Sivagnanam Parthasarathy | 2024-09-10 |
| 12086028 | Reduction of errors in data retrieved from a memory device to apply an error correction code of a predetermined code rate | Sivagnanam Parthasarathy, Kishore Kumar Muchherla, Akira Goda | 2024-09-10 |
| 12057185 | Voltage calibration scans to reduce memory device overhead | Kishore Kumar Muchherla, Sivagnanam Parthasarathy, Xiangang Luo, Peter Feeley, Devin M. Batutis +4 more | 2024-08-06 |
| 12046298 | Managing compensation for charge coupling and lateral migration in memory devices | Patrick R. Khayat, Sivagnanam Parthasarathy | 2024-07-23 |
| 12046307 | Managing program verify voltage offsets for charge coupling and lateral migration compensation in memory devices | Patrick R. Khayat, Sivagnanam Parthasarathy | 2024-07-23 |
| 12032444 | Error correction with syndrome computation in a memory device | Patrick R. Khayat, Sivagnanam Parthasarathy | 2024-07-09 |
| 12014071 | Separation of parity columns in bit-flip decoding of low-density parity-check codes with pipelining and column parallelism | Eyal En Gad, Sivagnanam Parthasarathy, Yoav Weinberg | 2024-06-18 |