Issued Patents All Time
Showing 1–25 of 116 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12431202 | Memory read calibration based on memory device-originated metrics characterizing voltage distributions | Dung Viet Nguyen, Patrick R. Khayat, Shantilal Rayshi Doru, Hope Henry | 2025-09-30 |
| 12386515 | Modification of program voltage level with read or program-verify adjustment for improving reliability in memory devices | Peng Zhang, Lei Lin, Hanping Chen, Li-Te Chang, Murong Lang +1 more | 2025-08-12 |
| 12332743 | Efficient memory use to support soft information in bit flipping decoders | Mustafa N. Kaynak, Eyal En Gad, Sivagnanam Parthasarathy, Phong Sy Nguyen, Dung Viet Nguyen | 2025-06-17 |
| 12301254 | Early stopping of bit-flip low density parity check decoding based on syndrome weight | Eyal En Gad, Mustafa N. Kaynak, Yoav Weinberg, Sivagnanam Parthasarathy | 2025-05-13 |
| 12197743 | Parity protection in non-volatile memory | Xiangang Luo | 2025-01-14 |
| 12086058 | Self-seeded randomizer for data randomization in flash memory | Jianmin Huang | 2024-09-10 |
| 12067264 | Power efficient codeword scrambling in a non-volatile memory device | Eyal En Gad, Yoav Weinberg | 2024-08-20 |
| 12007837 | Redundancy metadata schemes for rain protection of large codewords | Sivagnanam Parthasarathy | 2024-06-11 |
| 11914510 | Layer interleaving in multi-layered memory | Mikai Chen, Charles See Yeung Kwong | 2024-02-27 |
| 11907580 | Corrective read of a memory device with reduced latency | Tao Liu, Ting Luo | 2024-02-20 |
| 11870461 | Failure-tolerant error correction layout for memory sub-systems | Wei-Cheng Wu, Zhenlei Shen | 2024-01-09 |
| 11782787 | Dynamic error control configuration for memory systems | Deping He | 2023-10-10 |
| 11775381 | Redundancy metadata schemes for RAIN protection of large codewords | Sivagnanam Parthasarathy | 2023-10-03 |
| 11768766 | Metadata aware copyback for memory devices | Jianmin Huang | 2023-09-26 |
| 11750218 | Iterative error correction with adjustable parameters after a threshold number of iterations | Eyal En Gad, Sivagnanam Parthasarathy, Yoav Weinberg | 2023-09-05 |
| 11726671 | Memory access mode selection | Guang Hu, Jianmin Huang | 2023-08-15 |
| 11709771 | Self-seeded randomizer for data randomization in flash memory | Jianmin Huang | 2023-07-25 |
| 11688485 | Self-adaptive read voltage adjustment using boundary error statistics for memories with time-varying error rates | Tingjun Xie | 2023-06-27 |
| 11688467 | Defect detection in memories with time-varying bit error rate | Sai Krishna Mylavarapu, Zhenlei Shen, Tingjun Xie, Charles See Yeung Kwong | 2023-06-27 |
| 11632132 | Configuring iterative error correction parameters using criteria from previous iterations | Eyal En Gad, Sivagnanam Parthasarathy, Yoav Weinberg | 2023-04-18 |
| 11625299 | Inserting temperature information into a codeword | Stephen Hanna | 2023-04-11 |
| 11615830 | Performing a refresh operation based on a characteristic of a memory sub-system | Tingjun Xie, Seungjune Jeon, Zhenlei Shen, Charles See Yeung Kwong | 2023-03-28 |
| 11579809 | Performing a refresh operation based on a write to read time difference | Tingjun Xie | 2023-02-14 |
| 11561734 | Selecting read voltage using write transaction data | Tingjun Xie | 2023-01-24 |
| 11545230 | Manufacturer self-test for solid-state drives | David Patmore, Yingji Ju, Erich F. Haratsch | 2023-01-03 |