SH

Stephen Hanna

Micron: 25 patents #718 of 6,345Top 15%
IBM: 25 patents #4,217 of 70,183Top 7%
ST Seagate Technology: 10 patents #565 of 4,626Top 15%
IC Infoprint Solutions Company: 5 patents #16 of 167Top 10%
3S 3D Systems: 3 patents #101 of 374Top 30%
Lsi Logic: 2 patents #799 of 1,957Top 45%
VA Vantico: 1 patents #29 of 104Top 30%
Infineon Technologies Ag: 1 patents #4,439 of 7,486Top 60%
CC Ciba Specialty Chemicals: 1 patents #701 of 1,233Top 60%
Overall (All Time): #22,417 of 4,157,543Top 1%
80
Patents All Time

Issued Patents All Time

Showing 25 most recent of 80 patents

Patent #TitleCo-InventorsDate
12373808 Electronic device and method of operating an electronic device Theodore Varelas 2025-07-29
12353723 Low-power boot-up for memory systems Reshmi Basu, Jonathan S. Parry, David Aaron Palmer, Luca Porzio, Giuseppe Cariello 2025-07-08
12271317 Creating high density logical to physical mapping 2025-04-08
12216943 Integrated pivot table in a logical-to-physical mapping Giuseppe D'Eliseo, Luca Porzio 2025-02-04
12135887 Sequential data optimized sub-regions in storage devices David Aaron Palmer, Sean L. Manion, Jonathan S. Parry, Qing Liang, Nadav Grosz +2 more 2024-11-05
12124738 Address verification at a memory system 2024-10-22
12056518 Notifying memory system of host events via modulated reset signals Qing Liang, Jonathan S. Parry, Kulachet Tanpairoj 2024-08-06
11994951 Device reset alert mechanism 2024-05-28
11940926 Creating high density logical to physical mapping 2024-03-26
11941300 Integrated pivot table in a logical-to-physical mapping Giuseppe D'Eliseo, Luca Porzio 2024-03-26
11815939 Low cost and low latency logical unit erase 2023-11-14
11809311 Host-based flash memory maintenance techniques David Aaron Palmer, Christian M. Gyllenskog, Jonathan S. Parry 2023-11-07
11775207 Techniques to perform a write operation 2023-10-03
11755214 Sequential data optimized sub-regions in storage devices David Aaron Palmer, Sean L. Manion, Jonathan S. Parry, Qing Liang, Nadav Grosz +2 more 2023-09-12
11716096 Memory error correction based on layered error detection 2023-08-01
11704256 Facilitating sequential reads in memory sub-systems Nadav Grosz 2023-07-18
11687477 Signaling mechanism for bus inversion Jonathan S. Parry 2023-06-27
11656673 Managing reduced power memory operations Qing Liang, Jonathan S. Parry, David Aaron Palmer 2023-05-23
11625299 Inserting temperature information into a codeword Zhengang Chen 2023-04-11
11568953 Electrical device with test interface 2023-01-31
11520525 Integrated pivot table in a logical-to-physical mapping having entries and subsets associated via a flag Giuseppe D'Eliseo, Luca Porzio 2022-12-06
11513835 Notifying memory system of host events via modulated reset signals Qing Liang, Jonathan S. Parry, Kulachet Tanpairoj 2022-11-29
11347659 Low cost and low latency logical unit erase 2022-05-31
11329673 Memory error correction based on layered error detection 2022-05-10
11294838 Signaling mechanism for bus inversion Jonathan S. Parry 2022-04-05