Issued Patents All Time
Showing 25 most recent of 35 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12353770 | Adaptive block mapping | Alberto Sassara, Lalla Fatima Drissi, Luigi Esposito, Paolo Papa, Salvatore Del Prete +2 more | 2025-07-08 |
| 12321594 | Clustered parity for NAND data placement schema | Paolo Papa, Carminantonio Manganelli, Massimo Iaculo, Alberto Sassara | 2025-06-03 |
| 12293101 | Data relocation operation techniques | Paolo Papa, Luigi Esposito, Massimo Iaculo, Alberto Sassara, Carminantonio Manganelli +1 more | 2025-05-06 |
| 12277979 | NAND data placement schema | Carminantonio Manganelli, Paolo Papa, Massimo Iaculo, Alberto Sassara | 2025-04-15 |
| 12216943 | Integrated pivot table in a logical-to-physical mapping | Luca Porzio, Stephen Hanna | 2025-02-04 |
| 12183407 | Setting switching for single-level cells | Umberto Siciliani, Tao Liu, Ting Luo, Dionisio Minopoli, Giuseppe Ferrari +6 more | 2024-12-31 |
| 12073113 | Direct logical-to-physical address mapping for sequential physical addresses | Lalla Fatima Drissi, Doriana Tardio, Giuseppe Ferrari | 2024-08-27 |
| 12056046 | Corrupted storage portion recovery in a memory device | Lalla Fatima Drissi, Paolo Papa, Massimo Iaculo, Carminantonio Manganelli | 2024-08-06 |
| 11955189 | NAND data placement schema | Carminantonio Manganelli, Paolo Papa, Massimo Iaculo, Alberto Sassara | 2024-04-09 |
| 11941300 | Integrated pivot table in a logical-to-physical mapping | Luca Porzio, Stephen Hanna | 2024-03-26 |
| 11922053 | NAND logical-to-physical table region tracking | Eric Kwok Fung Yuen, Giuseppe Ferrari, Massimo Iaculo, Lalla Fatima Drissi, Xinghui Duan | 2024-03-05 |
| 11922069 | Adaptive block mapping | Alberto Sassara, Lalla Fatima Drissi, Luigi Esposito, Paolo Papa, Salvatore Del Prete +2 more | 2024-03-05 |
| 11907556 | Data relocation operation techniques | Paolo Papa, Luigi Esposito, Massimo Iaculo, Alberto Sassara, Carminantonio Manganelli +1 more | 2024-02-20 |
| 11886346 | Cache read context switching in a memory sub-system | Anna Scalesse, Umberto Siciliani, Carminantonio Manganelli | 2024-01-30 |
| 11733892 | Partial superblock memory management | Xiangang Luo, Ashutosh Malshe, Huachen Li, Jianmin Huang | 2023-08-22 |
| 11720489 | Scheme to improve efficiency of device garbage collection in memory devices | Xinghui Duan, Lalla Fatima Drissi, Giuseppe Ferrari, Eric Kwok Fung Yuen, Massimo Iaculo | 2023-08-08 |
| 11675709 | Reading sequential data from memory using a pivot table | Carminantonio Manganelli, Paolo Papa, Yoav Weinberg, Giuseppe Ferrari, Massimo Iaculo +1 more | 2023-06-13 |
| 11675411 | Dynamic P2L asynchronous power loss mitigation | Xiangang Luo, Ting Luo, Jianmin Huang | 2023-06-13 |
| 11663120 | Controlling NAND operation latency | Luigi Esposito, Xinghui Duan, Lucia Santojanni, Massimo Iaculo | 2023-05-30 |
| 11650931 | Hybrid logical to physical caching scheme of L2P cache and L2P changelog | Carminantonio Manganelli, Yoav Weinberg, Alberto Sassara, Paolo Papa, Luigi Esposito +2 more | 2023-05-16 |
| 11635894 | Clustered parity for NAND data placement schema | Paolo Papa, Carminantonio Manganelli, Massimo Iaculo, Alberto Sassara | 2023-04-25 |
| 11521690 | NAND data placement schema | Carminantonio Manganelli, Paolo Papa, Massimo Iaculo, Alberto Sassara | 2022-12-06 |
| 11520525 | Integrated pivot table in a logical-to-physical mapping having entries and subsets associated via a flag | Luca Porzio, Stephen Hanna | 2022-12-06 |
| 11455245 | Scheme to improve efficiency of garbage collection in cached flash translation layer | Xinghui Duan, Lalla Fatima Drissi, Giuseppe Ferrari, Eric Kwok Fung Yuen, Massimo Iaculo | 2022-09-27 |
| 11341041 | Synchronizing NAND logical-to-physical table region tracking | Zhao Cui, Eric Kwok Fung Yuen, Guan Wang, Xinghui Duan, Giuseppe Ferrari | 2022-05-24 |