Issued Patents All Time
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12353770 | Adaptive block mapping | Alberto Sassara, Giuseppe D'Eliseo, Lalla Fatima Drissi, Paolo Papa, Salvatore Del Prete +2 more | 2025-07-08 |
| 12293101 | Data relocation operation techniques | Paolo Papa, Massimo Iaculo, Giuseppe D'Eliseo, Alberto Sassara, Carminantonio Manganelli +1 more | 2025-05-06 |
| 12183407 | Setting switching for single-level cells | Umberto Siciliani, Tao Liu, Ting Luo, Dionisio Minopoli, Giuseppe D'Eliseo +6 more | 2024-12-31 |
| 11922069 | Adaptive block mapping | Alberto Sassara, Giuseppe D'Eliseo, Lalla Fatima Drissi, Paolo Papa, Salvatore Del Prete +2 more | 2024-03-05 |
| 11907556 | Data relocation operation techniques | Paolo Papa, Massimo Iaculo, Giuseppe D'Eliseo, Alberto Sassara, Carminantonio Manganelli +1 more | 2024-02-20 |
| 11705201 | Log data storage for flash memory | Paolo Papa, Massimo Iaculo, Eric Kwok Fung Yuen, Gerard J. Perdaems | 2023-07-18 |
| 11698826 | Fatal error logging in a memory device | Paolo Papa, Massimo Iaculo, Erika Morvillo | 2023-07-11 |
| 11662935 | Adaptive data relocation for improved data management for memory | Alberto Sassara, Paolo Papa, Massimo Iaculo | 2023-05-30 |
| 11663120 | Controlling NAND operation latency | Giuseppe D'Eliseo, Xinghui Duan, Lucia Santojanni, Massimo Iaculo | 2023-05-30 |
| 11650931 | Hybrid logical to physical caching scheme of L2P cache and L2P changelog | Carminantonio Manganelli, Yoav Weinberg, Alberto Sassara, Paolo Papa, Giuseppe D'Eliseo +2 more | 2023-05-16 |
| 11169917 | Controlling NAND operation latency | Giuseppe D'Eliseo, Xinghui Duan, Lucia Santojanni, Massimo Iaculo | 2021-11-09 |
| 11106521 | Fatal error logging in a memory device | Paolo Papa, Massimo Iaculo, Erika Morvillo | 2021-08-31 |
| 11100996 | Log data storage for flash memory | Paolo Papa, Massimo Iaculo, Eric Kwok Fung Yuen, Gerard J. Perdaems | 2021-08-24 |
| 10983918 | Hybrid logical to physical caching scheme | Carminantonio Manganelli, Yoav Weinberg, Alberto Sassara, Paolo Papa, Giuseppe D'Eliseo +2 more | 2021-04-20 |
| 10552316 | Controlling NAND operation latency | Giuseppe D'Eliseo, Xinghui Duan, Lucia Santojanni, Massimo Iaculo | 2020-02-04 |
| 9824882 | Method for manufacturing a protective layer against HF etching, semiconductor device provided with the protective layer and method for manufacturing the semiconductor device | Stefano Losa, Raffaella Pezzuto, Roberto Campedelli, Matteo Perletti, Mikel Azpeitia Urquia | 2017-11-21 |
| 9758373 | Method for manufacturing a protective layer against HF etching, semiconductor device provided with the protective layer and method for manufacturing the semiconductor device | Stefano Losa, Raffaella Pezzuto, Roberto Campedelli, Matteo Perletti, Mikel Azpeitia Urquia | 2017-09-12 |
| 9352955 | MEMS pressure sensor with improved insensitivity to thermo-mechanical stress | Antonio Molfese, Luca Coronato, Gabriele Cazzaniga | 2016-05-31 |
| 8669141 | Capped integrated device with protective cap, composite wafer incorporating integrated devices and process for bonding integrated devices with respective protective caps | Alessandro Freguglia | 2014-03-11 |
| 8634862 | Cross-architecture flight tracking system | Antonietta Libonati, Nico Vassallo | 2014-01-21 |
| 8415754 | Capped integrated device with protective cap, composite wafer incorporating integrated devices and process for bonding integrated devices with respective protective caps | Alessandro Freguglia | 2013-04-09 |