Issued Patents All Time
Showing 1–25 of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12431197 | Programming operation using cache register release in a memory sub-system | Walter Di Francesco, Violante Moschiano | 2025-09-30 |
| 12411770 | Hybrid parallel programming of single-level cell memory | Violante Moschiano, Walter Di Francesco | 2025-09-09 |
| 12380931 | Cross-temperature compensation in a memory sub-system | Andrea Giovanni Xotta, Tommaso Vali | 2025-08-05 |
| 12374404 | Algorithm qualifier commands | Anna Chiara Siviero | 2025-07-29 |
| 12340851 | Memories for performing successive programming operations | Violante Moschiano, Walter Di Francesco, Dheeraj Srinivasan | 2025-06-24 |
| 12327595 | Shortened single-level cell memory programming | Leo Raimondo, Federica Paolini, Violante Moschiano, Gianfranco Valeri, Davide Esposito +1 more | 2025-06-10 |
| 12271592 | Independent plane architecture in a memory device | Andrea Giovanni Xotta, Dheeraj Srinivasan, Ali Mohammadzadeh, Karl D. Schuh, Guido Luciano Rizzo +7 more | 2025-04-08 |
| 12189993 | Memory devices for suspend and resume operations | Floriano Montemurro | 2025-01-07 |
| 12183407 | Setting switching for single-level cells | Tao Liu, Ting Luo, Dionisio Minopoli, Giuseppe D'Eliseo, Giuseppe Ferrari +6 more | 2024-12-31 |
| 12068034 | Two-pass corrective programming for memory cells that store multiple bits and power loss management for two-pass corrective programming | Kishore Kumar Muchherla, Huai-Yuan Tseng, Giovanni Maria Paolucci, Dave Scott Ebsen, James Fitzpatrick +5 more | 2024-08-20 |
| 12001336 | Hybrid parallel programming of single-level cell memory | Violante Moschiano, Walter Di Francesco | 2024-06-04 |
| 11967384 | Algorithm qualifier commands | Anna Chiara Siviero | 2024-04-23 |
| 11966289 | Cross-temperature compensation in non-volatile memory devices | Andrea Giovanni Xotta | 2024-04-23 |
| 11908523 | Express programming using advanced cache register release in a memory sub-system | Walter Di Francesco, Violante Moschiano | 2024-02-20 |
| 11907574 | Memory devices for suspend and resume operations | Floriano Montemurro | 2024-02-20 |
| 11886346 | Cache read context switching in a memory sub-system | Giuseppe D'Eliseo, Anna Scalesse, Carminantonio Manganelli | 2024-01-30 |
| 11842078 | Asynchronous interrupt event handling in multi-plane memory devices | Andrea Giovanni Xotta, Guido Luciano Rizzo, Tommaso Vali, Luca De Santis, Walter Di Francesco | 2023-12-12 |
| 11740987 | Automatic chip initialization retry | Domenico Monteleone | 2023-08-29 |
| 11735268 | Memory devices for suspend and resume operations | Floriano Montemurro, Eric N. Lee, Dheeraj Srinivasan | 2023-08-22 |
| 11704047 | Temperature readings for memory devices to reduce temperature compensation errors | Agostino Macerola, Michele Piccardi, Tommaso Vali, Enrico Favaro | 2023-07-18 |
| 11550717 | Apparatuses and methods for concurrently accessing different memory planes of a memory | Tommaso Vali, Andrea Giovanni Xotta, Luca DeSantis, Michele Incarnati | 2023-01-10 |
| 11163572 | Memory systems and memory control methods | Tommaso Vali, Walter Di-Francesco, Violante Moschiano, Andrea Smaniotto | 2021-11-02 |
| 10922220 | Read and program operations in a memory device | Giulio Marotta, Tommaso Vali, Luca De Santis, Agostino Macerola, Violante Moshciano +3 more | 2021-02-16 |
| 10585606 | Memory device configuration commands | Anna Chiara Siviero, Andrea Smaniotto | 2020-03-10 |
| 10402319 | Apparatuses and methods for concurrently accessing different memory planes of a memory | Tommaso Vali, Andrea Giovanni Xotta, Luca DeSantis, Michele Incarnati | 2019-09-03 |