Issued Patents All Time
Showing 1–25 of 100 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12387781 | Corrective reads with improved recovery from data retention loss | Akira Goda, Ching-Huang Lu, Eric N. Lee, Tomoharu Tanaka | 2025-08-12 |
| 12380954 | Dynamic 1-tier scan for high performance 3D NAND | Xiang Yang, Deepanshu Dutta | 2025-08-05 |
| 12334154 | Write-once memory encoded data | Xiangyu Tang, Eric N. Lee, Akira Goda, Kishore Kumar Muchherla, Haibo Li | 2025-06-17 |
| 12334153 | Adaptive pre-read management in multi-pass programming | Kishore Kumar Muchherla, Akira Goda, Dung Viet Nguyen, Giovanni Maria Paolucci, James Fitzpatrick +3 more | 2025-06-17 |
| 12322450 | Memory programming using consecutive coarse-fine programming operations of threshold voltage distributions | Giovanni Maria Paolucci, Kishore Kumar Muchherla, James Fitzpatrick, Akira Goda | 2025-06-03 |
| 12307090 | Memory device programming technique for increased bits per cell | Tomoharu Tanaka, Dung Viet Nguyen, Kishore Kumar Muchherla, Eric N. Lee, Akira Goda +2 more | 2025-05-20 |
| 12266407 | Conditional valley tracking during corrective reads | Tomoharu Tanaka, James Fitzpatrick, Kishore Kumar Muchherla, Eric N. Lee, David Scott Ebsen +2 more | 2025-04-01 |
| 12249364 | Apparatus with non-linear delay variations for scheduling memory refresh operations and methods for operating the same | Akira Goda, Kishore Kumar Muchherla, James Fitzpatrick, Tomoharu Tanaka, Eric N. Lee +2 more | 2025-03-11 |
| 12131060 | Quick charge loss mitigation using two-pass controlled delay | Kishore Kumar Muchherla, Dung Viet Nguyen, Dave Scott Ebsen, Tomoharu Tanaka, James Fitzpatrick +2 more | 2024-10-29 |
| 12068034 | Two-pass corrective programming for memory cells that store multiple bits and power loss management for two-pass corrective programming | Kishore Kumar Muchherla, Giovanni Maria Paolucci, Dave Scott Ebsen, James Fitzpatrick, Akira Goda +5 more | 2024-08-20 |
| 12051467 | Programming of memory cells using a memory string dependent program voltage | Henry Chin, Deepanshu Dutta | 2024-07-30 |
| 11994947 | Multi-layer code rate architecture for special event protection with reduced performance penalty | Kishore Kumar Muchherla, Mustafa N. Kaynak, Akira Goda, Sivagnanam Parthasarathy, Jonathan S. Parry | 2024-05-28 |
| 11960722 | Memory device programming technique for increased bits per cell | Tomoharu Tanaka, Dung Viet Nguyen, Kishore Kumar Muchherla, Eric N. Lee, Akira Goda +2 more | 2024-04-16 |
| 11790992 | State dependent VPVD voltages for more uniform threshold voltage distributions in a memory device | Yu-Chung Lien | 2023-10-17 |
| 11758718 | Three dimensional memory device containing truncated channels and method of operating the same with different erase voltages for different bit lines | Yu-Chung Lien, Abhijith Prakash, Keyur Payak, Jiahui Yuan, Shinsuke Yada +1 more | 2023-09-12 |
| 11699494 | Peak and average ICC reduction by tier-based sensing during program verify operations of non-volatile memory structures | Xue Bai Pitner, Yu-Chung Lien, Deepanshu Dutta, Ravi Kumar | 2023-07-11 |
| 11636905 | Temperature compensation for unselected sub-block inhibit bias for mitigating erase disturb | Sarath Puthenthermadam | 2023-04-25 |
| 11600343 | Efficient read of NAND with read disturb mitigation | Yu-Chung Lien, Tomer Eliash | 2023-03-07 |
| 11532370 | Non-volatile memory with fast multi-level program verify | Xiang Yang, Deepanshu Dutta | 2022-12-20 |
| 11521677 | Memory apparatus and method of operation using negative kick clamp for fast read | Xiang Yang | 2022-12-06 |
| 11521686 | Memory apparatus and method of operation using state bit-scan dependent ramp rate for peak current reduction during program operation | Yu-Chung Lien, Hua-Ling Cynthia Hsu, Fanglin Zhang | 2022-12-06 |
| 11514991 | Program tail plane comparator for non-volatile memory structures | Fanqi Wu, Hua-Ling Cynthia Hsu, Deepanshu Dutta | 2022-11-29 |
| 11508450 | Dual time domain control for dynamic staggering | Yu-Chung Lien, Deepanshu Dutta | 2022-11-22 |
| 11475958 | Negative bit line biasing during quick pass write programming | Yu-Chung Lien, Swaroop Kaza, Tomer Eliash | 2022-10-18 |
| 11437110 | Erase tail comparator scheme | Fanqi Wu, Deepanshu Dutta | 2022-09-06 |