Issued Patents All Time
Showing 1–25 of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12362012 | Mixed bitline lockout for QLC/TLC die | Xiang Yang | 2025-07-15 |
| 12254931 | Three-bit-per-cell programming using a four-bit-per-cell programming algorithm | Xiang Yang, Deepanshu Dutta, Jiacen Guo, Takayuki Inoue | 2025-03-18 |
| 12197783 | Command and address sequencing in parallel with data operations | Fanglin Zhang | 2025-01-14 |
| 12057188 | Use of data latches for plane level compression of soft bit data in non-volatile memories | Siddarth Naga Murty Bassa, YenLung Li | 2024-08-06 |
| 12009049 | Non-volatile memory with shared data transfer latches | YenLung Li, Siddarth Naga Murty Bassa, Jeongduk Sohn | 2024-06-11 |
| 11971826 | Architecture and data path options for compression of soft bit data in non-volatile memories | A. Harihara Sravan, YenLung Li | 2024-04-30 |
| 11971829 | On-the-fly compression scheme for soft bit data in non-volatile memory | A. Harihara Sravan, YenLung Li | 2024-04-30 |
| 11966621 | Non-volatile storage system with program execution decoupled from dataload | Aaron Lee | 2024-04-23 |
| 11935599 | Burst programming of a NAND flash cell | Fanglin Zhang, Victor Avila | 2024-03-19 |
| 11907545 | On-the-fly multiplexing scheme for compressed soft bit data in non-volatile memories | YenLung Li, Siddarth Naga Murty Bassa, Chen Chen | 2024-02-20 |
| 11901019 | Use of data latches for compression of soft bit data in non-volatile memories | Masaaki Higashitani, YenLung Li, Chen Chen | 2024-02-13 |
| 11894068 | Efficient sensing of soft bit data for non-volatile memory | — | 2024-02-06 |
| 11776589 | Vertical compression scheme for compressed soft bit data in non-volatile memories with data latch groups | YenLung Li | 2023-10-03 |
| 11755211 | Overhead reduction in data transfer protocol for NAND memory | Grishma Shah, Daniel Tuers, Sahil Sharma, YenLung Li, Min Peng | 2023-09-12 |
| 11735288 | Non-volatile storage system with power on read timing reduction | YenLung Li | 2023-08-22 |
| 11705203 | Digital temperature compensation filtering | Henry Chin, Wei Zhao, Fanglin Zhang | 2023-07-18 |
| 11605436 | Countermeasure modes to address neighbor plane disturb condition in non-volatile memory structures | Henry Chin, Liang Li, Xuan Tian, Fanglin Zhang, Guanhua Yin | 2023-03-14 |
| 11521686 | Memory apparatus and method of operation using state bit-scan dependent ramp rate for peak current reduction during program operation | Yu-Chung Lien, Huai-Yuan Tseng, Fanglin Zhang | 2022-12-06 |
| 11521691 | Triggering next state verify in program loop for nonvolatile memory | Henry Chin, Han-Ping Chen, Erika Penzo, Fanglin Zhang | 2022-12-06 |
| 11514991 | Program tail plane comparator for non-volatile memory structures | Fanqi Wu, Deepanshu Dutta, Huai-Yuan Tseng | 2022-11-29 |
| 11487446 | Overhead reduction in data transfer protocol for NAND memory | Grishma Shah, Daniel Tuers, Sahil Sharma, YenLung Li, Min Peng | 2022-11-01 |
| 11373710 | Time division peak power management for non-volatile storage | Yu-Chung Lien, Mark Murin, Mark Shlick | 2022-06-28 |
| 11226772 | Peak power reduction management in non-volatile storage by delaying start times operations | Yu-Chung Lien, Mark Murin, Tomer Eliash, Huai-Yuan Tseng, Deepanshu Dutta | 2022-01-18 |
| 11211127 | Loop dependent plane skew methodology for program operation | Yu-Chung Lien, Huai-Yuan Tseng | 2021-12-28 |
| 11004535 | Robust storage of bad column data and parity bits on word line | YenLung Li, Aaron Lee | 2021-05-11 |