Issued Patents All Time
Showing 25 most recent of 43 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12393845 | Non-volatile memory die with deep learning neural network | Rami Rom, Ofir Pele, Alexander Bazarsky, Ran Zamir, Karin Inbar | 2025-08-19 |
| 12373116 | Dynamic read retry voltage sequences in a memory subsystem | Yu-Chung Lien, Zhenming Zhou | 2025-07-29 |
| 12314590 | Incomplete superblock management for memory systems | — | 2025-05-27 |
| 12306712 | Data storage device and method for identifying a failing area of memory based on a cluster of bit errors | Eran Sharon, Daniel Linnen, James Tom, Nika Yanuka, Preston A. Thomson +1 more | 2025-05-20 |
| 12242722 | Underfill detection for memory systems | Sead Zildzic | 2025-03-04 |
| 12106812 | Detecting a memory write reliability risk without using a write verify operation | Yu-Chung Lien, Zhenming Zhou | 2024-10-01 |
| 12067255 | Error detection for programming single level cells | Yu-Chung Lien | 2024-08-20 |
| 11941276 | Incomplete superblock management for memory systems | — | 2024-03-26 |
| 11907583 | Multiple sets of trim parameters | Asaf Gueta, Inon Cohen, Yuval Grossman | 2024-02-20 |
| 11868646 | Read level tracking by random threshold movement with short feedback loop | Alexander Bazarsky, Eran Sharon | 2024-01-09 |
| 11756637 | Block erase type detection using bit count check | Michael Ionin, Lior Avital, Lola Grin, Alexander Bazarsky, Itay BUSNACH +2 more | 2023-09-12 |
| 11705191 | Non-volatile memory die with deep learning neural network | Rami Rom, Ofir Pele, Alexander Bazarsky, Ran Zamir, Karin Inbar | 2023-07-18 |
| 11664075 | Sub-block programming mode with multi-tier block | Yu-Chung Lien, Jiahui Yuan | 2023-05-30 |
| 11619984 | Efficient power management modes for multiple memory devices | Alexander Bazarsky, Yuval Grossman | 2023-04-04 |
| 11600343 | Efficient read of NAND with read disturb mitigation | Yu-Chung Lien, Huai-Yuan Tseng | 2023-03-07 |
| 11593198 | Data storage system for improving data throughput and decode capabilities | Shemmer Choresh | 2023-02-28 |
| 11488682 | Calibration for integrated memory assembly | Alexander Bazarsky, Eran Sharon | 2022-11-01 |
| 11475958 | Negative bit line biasing during quick pass write programming | Yu-Chung Lien, Huai-Yuan Tseng, Swaroop Kaza | 2022-10-18 |
| 11449428 | Enhanced read-ahead capability for storage devices | Shay Benisty, Ariel Navon | 2022-09-20 |
| 11442635 | Data storage systems and methods for optimized scheduling of background management operations | Alexander Bazarsky, Yuval Grossman | 2022-09-13 |
| 11435914 | Dynamic ZNS open zone active limit | Alexander Bazarsky, Judah Gamliel Hahn, Ariel Navon, Shay Benisty | 2022-09-06 |
| 11416175 | Multiple sets of trim parameters | Asaf Gueta, Inon Cohen, Yuval Grossman | 2022-08-16 |
| 11386968 | Memory apparatus and method of operation using plane dependent ramp rate and timing control for program operation | Yu-Chung Lien, Huai-Yuan Tseng | 2022-07-12 |
| 11288011 | Non-volatile memory array with write failure protection for multi-level cell (MLC) storage elements using coupled writes | Alexander Bazarsky | 2022-03-29 |
| 11226772 | Peak power reduction management in non-volatile storage by delaying start times operations | Yu-Chung Lien, Mark Murin, Hua-Ling Cynthia Hsu, Huai-Yuan Tseng, Deepanshu Dutta | 2022-01-18 |