Issued Patents All Time
Showing 25 most recent of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12431203 | Memory program-verify with adaptive sense time based on row location | Xiang Yang, Yi Song, Jiahui Yuan | 2025-09-30 |
| 12394489 | In-place write techniques without erase in a memory device | Xiang Yang, Shubhajit Mukherjee | 2025-08-19 |
| 12354681 | Channel pre-charge process in a memory device | Peng Zhang, Xiang Yang, Yanli Zhang | 2025-07-08 |
| 12254931 | Three-bit-per-cell programming using a four-bit-per-cell programming algorithm | Xiang Yang, Deepanshu Dutta, Takayuki Inoue, Hua-Ling Cynthia Hsu | 2025-03-18 |
| 12243591 | In-place write techniques without erase in a memory device | Xiang Yang, Takayuki Inoue | 2025-03-04 |
| 12229415 | Hole channel pre-charge to enable large-volume in-place data sanitization of non-volatile memory | Wei Cao, Xiang Yang | 2025-02-18 |
| 12205654 | MLC programming techniques in a memory device | Xiang Yang, Takayuki Inoue | 2025-01-21 |
| 12176037 | Non-volatile memory with different word line to word line pitches | Xiang Yang, Wei Cao | 2024-12-24 |
| 12142315 | Low power multi-level cell (MLC) programming in non-volatile memory structures | Xiang Yang, Muhammad Masuduzzaman | 2024-11-12 |
| 12119065 | Non-volatile memory with zoned control for limiting programming for different groups of non-volatile memory cells | Xiaochen Zhu, Lito De La Rama, Yi Song, Jiahui Yuan | 2024-10-15 |
| 12112812 | Non-volatile memory with early dummy word line ramp down after precharge | Dengtao Zhao, Xiang Yang | 2024-10-08 |
| 12112800 | High speed multi-level cell (MLC) programming in non-volatile memory structures | Xiang Yang, Deepanshu Dutta, Muhammad Masuduzzaman | 2024-10-08 |
| 12100461 | Non-volatile memory with suspension period during programming | Yi Song, Jiahui Yuan | 2024-09-24 |
| 11972813 | Systems and methods for adapting sense time | Xiang Yang, Swaroop Kaza, Laidong Wang | 2024-04-30 |
| 11972819 | Non-volatile memory with one sided phased ramp down after program-verify | Peng Zhang, Xiang Yang, Yanli Zhang | 2024-04-30 |
| 11972820 | Non-volatile memory with tier-wise ramp down after program-verify | Dengtao Zhao, Xiang Yang | 2024-04-30 |
| 11972806 | Read techniques to reduce read errors in a memory device | Xiang Yang | 2024-04-30 |
| 11955184 | Memory cell group read with compensation for different programming speeds | Xiaochen Zhu, Xiang Yang, Lito De La Rama, Yi Song, Jiahui Yuan | 2024-04-09 |
| 11942157 | Variable bit line bias for nonvolatile memory | Xiang Yang, Xiaochen Zhu | 2024-03-26 |
| 11923019 | Data retention reliability | Xiaojia Jia, Swaroop Kaza, Laidong Wang | 2024-03-05 |
| 11901016 | Fast open block erase in non-volatile memory structures | Xiaojia Jia | 2024-02-13 |
| 11894072 | Two-side staircase pre-charge in sub-block mode of three-tier non-volatile memory architecture | Xiang Yang, Abhijith Prakash | 2024-02-06 |
| 11881271 | Non-volatile memory with engineered channel gradient | Xiang Yang, Xiaochen Zhu | 2024-01-23 |
| 11862249 | Non-volatile memory with staggered ramp down at the end of pre-charging | Xiang Yang, Fanqi Wu, Jiahui Yuan | 2024-01-02 |
| 11862260 | Audit techniques for read disturb detection in an open memory block | Swaroop Kaza | 2024-01-02 |