Issued Patents All Time
Showing 25 most recent of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12424295 | Evolving bad block detection in non-volatile memory | Parth Amin, Xiang Yang | 2025-09-23 |
| 12394483 | Memory die management | Xiang Yang | 2025-08-19 |
| 12387800 | Multi-stage programming techniques with three states per memory cell parity | Xiang Yang | 2025-08-12 |
| 12379990 | Single block mode block handling for single-side GIDL erase | Xiang Yang | 2025-08-05 |
| 12354682 | Intermediate re-verify for achieving tighter threshold voltage distributions in a memory device | Xiang Yang | 2025-07-08 |
| 12327046 | Data retention-specific refresh read | Muhammad Masuduzzaman, Deepanshu Dutta | 2025-06-10 |
| 12230333 | Bit line modulation to compensate for cell source variation | Anirudh Amarnath, Aravind Suresh | 2025-02-18 |
| 12148478 | Erase method for non-volatile memory with multiple tiers | Xiang Yang, Masaaki Higashitani, Dengtao Zhao | 2024-11-19 |
| 12087363 | Control gate signal for data retention in nonvolatile memory | Anubhav Khandelwal | 2024-09-10 |
| 12046305 | Pre-position dummy word line to facilitate write erase capability of memory apparatus | Xiang Yang | 2024-07-23 |
| 11972818 | Refresh frequency-dependent system-level trimming of verify level offsets for non-volatile memory | Xiang Yang | 2024-04-30 |
| 11972808 | Recovery pulses to counter cumulative read disturb | Xiang Yang | 2024-04-30 |
| 11961573 | Memory device that is optimized for operation at different temperatures | Xiang Yang, Dengtao Zhao | 2024-04-16 |
| 11961572 | Edge word line data retention improvement for memory apparatus with on-pitch semi-circle drain side select gate technology | Xiang Yang, Shubhajit Mukherjee | 2024-04-16 |
| 11894067 | Method to fix cumulative read induced drain side select gate downshift in memory apparatus with on-pitch drain side select gate | Xiang Yang, Shubhajit Mukherjee | 2024-02-06 |
| 11894072 | Two-side staircase pre-charge in sub-block mode of three-tier non-volatile memory architecture | Jiacen Guo, Xiang Yang | 2024-02-06 |
| 11894051 | Temperature-dependent word line voltage and discharge rate for refresh read of non-volatile memory | Dong-Il Moon, Wei Zhao, Henry Chin | 2024-02-06 |
| 11848059 | Techniques for erasing the memory cells of edge word lines | Jiacen Guo, Xiang Yang | 2023-12-19 |
| 11758718 | Three dimensional memory device containing truncated channels and method of operating the same with different erase voltages for different bit lines | Yu-Chung Lien, Keyur Payak, Jiahui Yuan, Huai-Yuan Tseng, Shinsuke Yada +1 more | 2023-09-12 |
| 11605430 | Control gate signal for data retention in nonvolatile memory | Anubhav Khandelwal | 2023-03-14 |
| 11545226 | Systems and methods for compensating for erase speed variations due to semi-circle SGD | Xiang Yang | 2023-01-03 |
| 11501837 | Read operation or word line voltage refresh operation in memory device with reduced peak current | — | 2022-11-15 |
| 11482289 | Application based verify level offsets for non-volatile memory | Anubhav Khandelwal | 2022-10-25 |
| 11468950 | Memory programming with selectively skipped bitscans and fewer verify pulses for performance improvement | Anubhav Khandelwal | 2022-10-11 |
| 11456042 | Multi-level program pulse for programming single level memory cells to reduce damage | Xiang Yang, Jiahui Yuan | 2022-09-27 |