Issued Patents All Time
Showing 25 most recent of 30 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12108597 | Three-dimensional memory device containing a pillar contact between channel and source and methods of making the same | Teruo Okina, Ryo YOSHIMOTO | 2024-10-01 |
| 11935784 | Three-dimensional memory device containing self-aligned bit line contacts and methods for forming the same | Fumitaka Amano, Yusuke OSAWA, Kensuke Ishikawa, Mitsuteru Mushiga, Motoki KAWASAKI +4 more | 2024-03-19 |
| 11889684 | Three-dimensional memory device with separated source-side lines and method of making the same | Masanori Tsutsumi, Mitsuteru Mushiga, Akio Nishida, Hiroyuki Ogawa, Teruo Okina | 2024-01-30 |
| 11882702 | Lateral transistors for selecting blocks in a three-dimensional memory array and methods for forming the same | — | 2024-01-23 |
| 11758718 | Three dimensional memory device containing truncated channels and method of operating the same with different erase voltages for different bit lines | Yu-Chung Lien, Abhijith Prakash, Keyur Payak, Jiahui Yuan, Huai-Yuan Tseng +1 more | 2023-09-12 |
| 11626415 | Lateral transistors for selecting blocks in a three-dimensional memory array and methods for forming the same | Shogo Tomita | 2023-04-11 |
| 11501835 | Three-dimensional memory device and method of erasing thereof from a source side | Hiroyuki Ogawa | 2022-11-15 |
| RE49165 | On-pitch drain select level isolation structure for three-dimensional memory device and method of making the same | Yanli Zhang, Masanori Tsutsumi, Sayako Nagamine, Johann Alsmeier | 2022-08-09 |
| 11393836 | Three-dimensional memory device with separated source-side lines and method of making the same | Masanori Tsutsumi, Mitsuteru Mushiga, Akio Nishida, Hiroyuki Ogawa, Teruo Okina | 2022-07-19 |
| 11121153 | Three-dimensional memory devices containing structures for controlling gate-induced drain leakage current and method of making the same | Tomoyuki Obu | 2021-09-14 |
| 11049568 | Three-dimensional memory device with depletion region position control and method of erasing same using gate induced leakage | — | 2021-06-29 |
| 10957680 | Semiconductor die stacking using vertical interconnection by through-dielectric via structures and methods for making the same | Masanori Tsutsumi, Sayako Nagamine, Yuji Fukano, Akio Nishida, Christopher J. Petti | 2021-03-23 |
| 10692884 | Three-dimensional memory device including bottle-shaped memory stack structures and drain-select gate electrodes having cylindrical portions | Zhixin Cui, Kiyohiko Sakakibara | 2020-06-23 |
| 10600800 | Three-dimensional memory device containing multilevel drain select gate isolation and methods of making the same | Masatoshi Nishikawa, Yanli Zhang | 2020-03-24 |
| 10559582 | Three-dimensional memory device containing source contact to bottom of vertical channels and method of making the same | Masatoshi Nishikawa, Masanori Tsutsumi | 2020-02-11 |
| 10475804 | Three-dimensional memory device containing multilevel drain select gate isolation and methods of making the same | Masatoshi Nishikawa, Yanli Zhang | 2019-11-12 |
| 10381229 | Three-dimensional memory device with straddling drain select electrode lines and method of making thereof | Akihisa SAI, Kiyohiko Sakakibara | 2019-08-13 |
| 10381450 | Three-dimensional memory device with self-aligned drain select level isolation structures and method of making thereof | Xiaolong Hu, Junichi Ariyoshi | 2019-08-13 |
| 10297610 | Three-dimensional memory device having on-pitch drain select gate electrodes and method of making the same | James Kai, Johann Alsmeier, Akihisa SAI, Sayako Nagamine, Takashi Orimoto +1 more | 2019-05-21 |
| 10236300 | On-pitch drain select level isolation structure for three-dimensional memory device and method of making the same | Yanli Zhang, Masanori Tsutsumi, Sayako Nagamine, Johann Alsmeier | 2019-03-19 |
| 10192878 | Three-dimensional memory device with self-aligned multi-level drain select gate electrodes | Masanori Tsutsumi, Yanli Zhang | 2019-01-29 |
| 9876027 | Three dimensional NAND device with channel located on three sides of lower select gate and method of making thereof | Hiroyuki Ogawa | 2018-01-23 |
| 9793288 | Methods of fabricating memory device with spaced-apart semiconductor charge storage regions | Hiroyuki Kamiya | 2017-10-17 |
| 9754956 | Uniform thickness blocking dielectric portions in a three-dimensional memory structure | Masanori Tsutsumi | 2017-09-05 |
| 9716062 | Multilevel interconnect structure and methods of manufacturing the same | Hiroyuki Ogawa | 2017-07-25 |