Issued Patents All Time
Showing 1–25 of 52 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11763907 | Reverse VT-state operation and optimized BiCS device structure | — | 2023-09-19 |
| 11631691 | Three-dimensional flat memory device including a dual dipole blocking dielectric layer and methods of making the same | Masatoshi Nishikawa | 2023-04-18 |
| 11456044 | Reverse VT-state operation and optimized BiCS device structure | — | 2022-09-27 |
| 11348649 | Threshold voltage setting with boosting read scheme | Hiroki Yabe, Ken Oowada, Masaaki Higashitani | 2022-05-31 |
| 11342006 | Buried source line structure for boosting read scheme | Ken Oowada | 2022-05-24 |
| 11227663 | Boosting read scheme with back-gate bias | Ippei Yasuda, Ken Oowada, Masaaki Higashitani | 2022-01-18 |
| 11004518 | Threshold voltage setting with boosting read scheme | Hiroki Yabe, Ken Oowada, Masaaki Higashitani | 2021-05-11 |
| 10957401 | Boosting read scheme with back-gate bias | Ippei Yasuda, Ken Oowada, Masaaki Higashitani | 2021-03-23 |
| 10950311 | Boosting read scheme with back-gate bias | Ippei Yasuda, Ken Oowada, Masaaki Higashitani | 2021-03-16 |
| 10916556 | Three-dimensional memory device using a buried source line with a thin semiconductor oxide tunneling layer | Takumi Moriyama, Yu-Hsien Hsu | 2021-02-09 |
| 10903222 | Three-dimensional memory device containing a carbon-doped source contact layer and methods for making the same | Masaaki Higashitani, Masanori Tsutsumi, Zhixin Cui | 2021-01-26 |
| 10854627 | Three-dimensional memory device containing a capped insulating source line core and method of making the same | Takumi Moriyama, Satoshi Shimizu | 2020-12-01 |
| 10777575 | Three-dimensional memory device with self-aligned vertical conductive strips having a gate-all-around configuration and method of making the same | Zhixin Cui, Yanli Zhang | 2020-09-15 |
| 10720444 | Three-dimensional flat memory device including a dual dipole blocking dielectric layer and methods of making the same | Masatoshi Nishikawa | 2020-07-21 |
| 10720445 | Three-dimensional memory device having nitrided direct source strap contacts and method of making thereof | Satoshi Shimizu, Takumi Moriyama | 2020-07-21 |
| 10692884 | Three-dimensional memory device including bottle-shaped memory stack structures and drain-select gate electrodes having cylindrical portions | Zhixin Cui, Shinsuke Yada | 2020-06-23 |
| 10629613 | Three-dimensional memory device having vertical semiconductor channels including source-side boron-doped pockets and methods of making the same | Satoshi Shimizu, Yu-Hsien Hsu | 2020-04-21 |
| 10629611 | Three-dimensional memory device and methods of making the same using replacement drain select gate electrodes | Zhixin Cui, Mitsuteru Mushiga, Hisakazu Otoi, Kenji Sugiura | 2020-04-21 |
| 10586803 | Three-dimensional memory device and methods of making the same using replacement drain select gate electrodes | Mitsuteru Mushiga, Hisakazu Otoi, Kenji Sugiura, Zhixin Cui | 2020-03-10 |
| 10381229 | Three-dimensional memory device with straddling drain select electrode lines and method of making thereof | Shinsuke Yada, Akihisa SAI | 2019-08-13 |
| 10304852 | Three-dimensional memory device containing through-memory-level contact via structures | Zhixin Cui, Tomohiro Kubo | 2019-05-28 |
| 10199359 | Three-dimensional memory device employing direct source contact and hole current detection and method of making the same | Satoshi Shimizu, Naoto Norizuki | 2019-02-05 |
| 10074661 | Three-dimensional junction memory device and method reading thereof using hole current detection | Yusuke Ikawa | 2018-09-11 |
| 9911748 | Epitaxial source region for uniform threshold voltage of vertical transistors in 3D memory devices | Masatoshi Nishikawa, Hiroyuki Ogawa, Shuji Minagawa | 2018-03-06 |
| 9812463 | Three-dimensional memory device containing vertically isolated charge storage regions and method of making thereof | Rahul Sharangpani, Raghuveer S. Makala, Senaka Kanakamedala, Fei Zhou, Somesh Peri +4 more | 2017-11-07 |