Hiroki Yabe — 39 Patents at Sandisk Technologies

Hiroki Yabe has been granted 39 US patents while listed as an inventor at Sandisk Technologies. The first was granted in 2004 and the most recent in June 2025. Hiroki Yabe ranks #81,245 of 4,157,543 US inventors in our database (top 2.0%). Patent records list Hiroki Yabe in Yokohama, CA, JP.

Issued Patents All Time

Showing 1–25 of 39 patents

Patent #	Title	Co-Inventors	Date	Approx Value ⓘ
12322452	Three-dimensional memory device including a bit-line-bias vertical transistor block and methods of operating the same	Naoto Norizuki	2025-06-03
12260921	Sense amplifier architecture providing reduced program verification time	—	2025-03-25
12040010	IR drop compensation for sensing memory	—	2024-07-16
11972807	Charge pump current regulation during voltage ramp	—	2024-04-30
11869600	Memory cell sensing by charge sharing between sensing nodes	Jiawei Xu, Anirudh Amarnath	2024-01-09
11777143	Solid electrolyte, electrode, power storage device, and method for producing solid electrolytes	Xubin Chen, Knut Bjarne Gandrud, Maarten Mees, Philippe M. Vereecken, AKIHIKO SAGARA +1 more	2023-10-03
11610625	Hetero-plane data storage structures for non-volatile memory	—	2023-03-21
11573914	Nonconsecutive mapping scheme for data path circuitry in a storage device	Masahito Takehara	2023-02-07
11488669	Three-valued programming mechanism for non-volatile memory structures	Keiji Nose, Masahiro Kano, Yuki Fujita	2022-11-01
11405039	Level shifter with improved negative voltage capability	—	2022-08-02
11348649	Threshold voltage setting with boosting read scheme	Kiyohiko Sakakibara, Ken Oowada, Masaaki Higashitani	2022-05-31
11336283	Level shifter with improved negative voltage capability	—	2022-05-17
11250920	Loop-dependent switching between program-verify techniques	—	2022-02-15
11177277	Word line architecture for three dimensional NAND flash memory	Naoki Ookuma, Koichiro Hayashi, Takuya Ariki, Toru Miwa	2021-11-16
11158384	Apparatus and methods for configurable bit line isolation in non-volatile memory	—	2021-10-26
11087800	Sense amplifier architecture providing small swing voltage sensing	—	2021-08-10
11081167	Sense amplifier architecture for low supply voltage operations	Koichiro Hayashi	2021-08-03
11081192	Memory plane structure for ultra-low read latency applications in non-volatile memories	Koichiro Hayashi, Takuya Ariki, Yuki Fujita, Naoki Ookuma, Kazuki Yamauchi +2 more	2021-08-03
11004518	Threshold voltage setting with boosting read scheme	Kiyohiko Sakakibara, Ken Oowada, Masaaki Higashitani	2021-05-11
10984874	Differential dbus scheme for low-latency random read for NAND memories	Koichiro Hayashi, Takuya Ariki, Naoki Ookuma, Toru Miwa	2021-04-20
10984877	Multi BLCS for multi-state verify and multi-level QPW	Jongyeon Kim, Kou Tei, Chia-Kai Chou, Ohwon Kwon	2021-04-20
10964390	Skip coding for fractional bit-per-cell NAND memories	—	2021-03-30	$27,477,000
10910044	State coding for fractional bits-per-cell memory	Masahiro Kano	2021-02-02
10885984	Area effective erase voltage isolation in NAND memory	Koichiro Hayashi, Takuya Ariki, Yuki Fujita, Naoki Ookuma, Kazuki Yamauchi +2 more	2021-01-05
10643677	Negative kick on bit line control transistors for faster bit line settling during sensing	—	2020-05-05

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Hiroki Yabe — 39 Patents

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