Issued Patents All Time
Showing 25 most recent of 48 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12387802 | Non-volatile memory with lower current program-verify | Abu Naser Zainuddin, Jiahui Yuan | 2025-08-12 |
| 12354664 | Non-volatile memory with loop dependant ramp-up rate | Abu Naser Zainuddin, Jiahui Yuan | 2025-07-08 |
| 12270853 | Semiconductor wafer configured for single touch-down testing | Takashi Murai, Hiroyuki Ogawa, Nisha Padattil Kuliyampattil | 2025-04-08 |
| 12230335 | Data latch programming algorithm for multi-bit-per-cell memory devices | Fumiaki Toyama | 2025-02-18 |
| 11875043 | Loop dependent word line ramp start time for program verify of multi-level NAND memory | Abu Naser Zainuddin, Jiahui Yuan | 2024-01-16 |
| 11625172 | Programming memory cells with concurrent redundant storage of data for power loss protection | Xiang Yang, Ken Oowada, Gerrit Jan Hemink | 2023-04-11 |
| 11551781 | Programming memory cells with concurrent storage of multi-level data as single-level data for power loss protection | Xiang Yang, Ken Oowada, Gerrit Jan Hemink | 2023-01-10 |
| 11545221 | Concurrent programming of multiple cells for non-volatile memory devices | Xiang Yang, Gerrit Jan Hemink, Ken Oowada | 2023-01-03 |
| 11342028 | Concurrent programming of multiple cells for non-volatile memory devices | Xiang Yang, Aaron Lee, Gerrit Jan Hemink, Ken Oowada | 2022-05-24 |
| 11177277 | Word line architecture for three dimensional NAND flash memory | Naoki Ookuma, Hiroki Yabe, Koichiro Hayashi, Takuya Ariki | 2021-11-16 |
| 11081192 | Memory plane structure for ultra-low read latency applications in non-volatile memories | Hiroki Yabe, Koichiro Hayashi, Takuya Ariki, Yuki Fujita, Naoki Ookuma +2 more | 2021-08-03 |
| 10984874 | Differential dbus scheme for low-latency random read for NAND memories | Hiroki Yabe, Koichiro Hayashi, Takuya Ariki, Naoki Ookuma | 2021-04-20 |
| 10978156 | Concurrent programming of multiple cells for non-volatile memory devices | Xiang Yang, Aaron Lee, Gerrit Jan Hemink, Ken Oowada | 2021-04-13 |
| 10885984 | Area effective erase voltage isolation in NAND memory | Hiroki Yabe, Koichiro Hayashi, Takuya Ariki, Yuki Fujita, Naoki Ookuma +2 more | 2021-01-05 |
| 10854619 | Three-dimensional memory device containing bit line switches | Hardwell Chibvongodze, Masatoshi Nishikawa, Naoki Ookuma, Takuya Ariki | 2020-12-01 |
| 10734080 | Three-dimensional memory device containing bit line switches | Hardwell Chibvongodze, Masatoshi Nishikawa, Naoki Ookuma, Takuya Ariki | 2020-08-04 |
| 10635526 | Multicore on-die memory microcontroller | Yibo Yin, Henry Zhang, Po-Shen Lai, Vijay Chinchole, Spyridon Georgakis +4 more | 2020-04-28 |
| 9941297 | Vertical resistor in 3D memory device with two-tier stack | Masatoshi Nishikawa, Kota Funayama, Hiroyuki Ogawa | 2018-04-10 |
| 9691781 | Vertical resistor in 3D memory device with two-tier stack | Masatoshi Nishikawa, Kota Funayama, Hiroyuki Ogawa | 2017-06-27 |
| 9646981 | Passive devices for integration with three-dimensional memory devices | Masatoshi Nishikawa, Ryoichi Honma, Masahide Matsumoto, Yuki Mizutani, Hiroaki Koketsu | 2017-05-09 |
| 9595535 | Integration of word line switches with word line contact via structures | Hiroyuki Ogawa, Makoto Yoshida, Kazutaka Yoshizawa, Takuya Ariki | 2017-03-14 |
| 9589981 | Passive devices for integration with three-dimensional memory devices | Masatoshi Nishikawa, Ryoichi Honma, Hiroaki Koketsu, Johann Alsmeier | 2017-03-07 |
| RE46264 | Verification process for non-volatile storage | Gerrit Jan Hemink, Shih-Chung Lee, Yupin Fong, Jun Wan, Ken Oowada | 2017-01-03 |
| RE46014 | Defective word line detection | Manabu Sakai | 2016-05-24 |
| 9142298 | Efficient smart verify method for programming 3D non-volatile memory | Yingda Dong, Cynthia Hsu, Man Lung Mui, Manabu Sakai, Masaaki Higashitani | 2015-09-22 |