Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12417809 | Open block read ICC reduction | Jiahui Yuan, Deepanshu Dutta | 2025-09-16 |
| 12394491 | Apparatus and method for selectively reducing charge pump speed during erase operations | Jiahui Yuan, Mark Shlick, Shemmer Choresh | 2025-08-19 |
| 12387802 | Non-volatile memory with lower current program-verify | Jiahui Yuan, Toru Miwa | 2025-08-12 |
| 12354664 | Non-volatile memory with loop dependant ramp-up rate | Jiahui Yuan, Toru Miwa | 2025-07-08 |
| 12346578 | Distributed temperature sensing scheme to suppress peak Icc in non-volatile memories | Jiahui Yuan, Sai Gautham Thoppa | 2025-07-01 |
| 12176032 | Word line dependent pass voltage ramp rate to improve performance of NAND memory | Jiahui Yuan, Towhidur Razzak | 2024-12-24 |
| 12099728 | Non-volatile memory with programmable resistance non-data word line | Towhidur Razzak, Ravi Kumar, Jiahui Yuan | 2024-09-24 |
| 12046314 | NAND memory with different pass voltage ramp rates for binary and multi-state memory | Jiahui Yuan, Dong-Il Moon | 2024-07-23 |
| 11875043 | Loop dependent word line ramp start time for program verify of multi-level NAND memory | Jiahui Yuan, Toru Miwa | 2024-01-16 |
| 11705206 | Modifying program and erase parameters for single-bit memory cells to improve single-bit/multi-bit hybrid ratio | Jia Li, Jiahui Yuan, Bo Lei | 2023-07-18 |
| 11475957 | Optimized programming with a single bit per memory cell and multiple bits per memory cell | Dongxiang Liao, Jiahui Yuan | 2022-10-18 |
| 11205493 | Controlling word line voltages to reduce read disturb in a memory device | Henry Chin, Jiahui Yuan | 2021-12-21 |
| 11139018 | Memory device with temporary kickdown of source voltage before sensing | Ohwon Kwon, Jiahui Yuan | 2021-10-05 |
| 10991689 | Additional spacer for self-aligned contact for only high voltage FinFETs | Christopher D. Sheraw, Sangameshwar Rao Saudari, Wei Ma, Kai Zhao, Bala Haran | 2021-04-27 |
| 10755982 | Methods of forming gate structures for transistor devices on an IC product | Wei-Yuan MA, Daniel Jaeger, Joseph Versaggi, Jae Gon Lee, Thomas Kauerauf | 2020-08-25 |
| 10438853 | Methods, apparatus and system for forming a FinFET device comprising a first portion capable of operating at a first voltage and a second portion capable of operating at a second voltage | Shahab Siddiqui, Beth Baumert, Luigi Pantisano | 2019-10-08 |
| 10106892 | Thermal oxide equivalent low temperature ALD oxide for dual purpose gate oxide and method for producing the same | Shahab Siddiqui, Beth Baumert, Suresh Uppal | 2018-10-23 |