Issued Patents All Time
Showing 1–25 of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12367931 | Stacked column floorplan for NAND | — | 2025-07-22 |
| 12243593 | Low power read method and a memory device capable thereof | Xiang Yang, Deepanshu Dutta, Ohwon Kwon, James Kai | 2025-03-04 |
| 12207459 | Three-dimensional memory array with dual-level peripheral circuits and methods for forming the same | Fumiaki Toyama, Masaaki Higashitani | 2025-01-21 |
| 12032837 | Non-volatile memory with reduced word line switch area | Kazutaka Yoshizawa, Kiyokazu Shishido, Eiichi Fujikura | 2024-07-09 |
| 12004348 | Three-dimensional memory array with dual-level peripheral circuits and methods for forming the same | Fumiaki Toyama, Masaaki Higashitani | 2024-06-04 |
| 11996153 | Three-dimensional memory device with separated contact regions and methods for forming the same | James Kai, Hisakazu Otoi, Masaaki Higashitani, Hiroyuki Ogawa | 2024-05-28 |
| 11569259 | Three-dimensional memory device with double-sided stepped surfaces and method of making thereof | Masaaki Higashitani | 2023-01-31 |
| 11404123 | Non-volatile memory with multiple wells for word line switch transistors | Shiqian Shao, Fumiaki Toyama, Mohan Dunga, Peter Rabkin | 2022-08-02 |
| 11355486 | Bonded three-dimensional memory devices and methods of making the same by replacing carrier substrate with source layer | Masaaki Higashitani, James Kai | 2022-06-07 |
| 11211370 | Bonded assembly with vertical power and control signal connection adjacent to sense amplifier regions and methods of forming the same | Jee-Yeon Kim, Fumiaki Toyama | 2021-12-28 |
| 11114459 | Three-dimensional memory device containing width-modulated connection strips and methods of forming the same | Takaaki Iwai, Hirofumi TOKITA, Yoshitaka Otsu, Fumiaki Toyama | 2021-09-07 |
| 11081443 | Multi-tier three-dimensional memory device containing dielectric well structures for contact via structures and methods of forming the same | Masayuki Hiroi, Fumiaki Toyama | 2021-08-03 |
| 11011209 | Three-dimensional memory device including contact-level bit-line-connection structures and methods of making the same | Jee-Yeon Kim, Kwang Ho Kim, Fumiaki Toyama | 2021-05-18 |
| 10903237 | Three-dimensional memory device including stepped connection plates and methods of forming the same | Naohiro Hosoda, Hiroyuki Ogawa | 2021-01-26 |
| 10381371 | Through-memory-level via structures for a three-dimensional memory device | Hiroyuki Ogawa, Fumiaki Toyama | 2019-08-13 |
| 10256248 | Through-memory-level via structures between staircase regions in a three-dimensional memory device and method of making thereof | Zhenyu Lu, Jixin Yu, Johann Alsmeier, Fumiaki Toyama, Hiroyuki Ogawa +5 more | 2019-04-09 |
| 9935050 | Multi-tier three-dimensional memory devices including vertically shared source lines and method of making thereof | Mohan Dunga, Zhenyu Lu | 2018-04-03 |
| 9929174 | Three-dimensional memory device having non-uniform spacing among memory stack structures and method of making thereof | Hiroyuki Ogawa, Fumiaki Toyama, Masaaki Higashitani, Fumitaka Amano, Kota Funayama +1 more | 2018-03-27 |
| 9922987 | Three-dimensional memory device containing separately formed drain select transistors and method of making thereof | James Kai, Fumiaki Toyama, Shigehiro Fujino, Johann Alsmeier | 2018-03-20 |
| 9818693 | Through-memory-level via structures for a three-dimensional memory device | Fumiaki Toyama, Hiroyuki Ogawa, Yoko Furihata, James Kai, Jixin Yu +2 more | 2017-11-14 |
| 9806093 | Through-memory-level via structures for a three-dimensional memory device | Fumiaki Toyama, Hiroyuki Ogawa | 2017-10-31 |
| 9768186 | Three dimensional memory device having well contact pillar and method of making thereof | Seiji Shimabukuro, Ryoichi Honma, Hiroyuki Ogawa, Fumiaki Toyama | 2017-09-19 |
| 9646981 | Passive devices for integration with three-dimensional memory devices | Masatoshi Nishikawa, Ryoichi Honma, Toru Miwa, Masahide Matsumoto, Hiroaki Koketsu | 2017-05-09 |
| 9613975 | Bridge line structure for bit line connection in a three-dimensional semiconductor device | Chenche Huang, Chun-Ming Wang, Hiroaki Koketsu, Masayuki Hiroi, Masaaki Higashitani | 2017-04-04 |
| 9595338 | Utilizing NAND strings in dummy blocks for faster bit line precharge | Juan Lee, Hao Thai Nguyen, Man Lung Mui, Tien-Chien Kuo | 2017-03-14 |