Issued Patents All Time
Showing 25 most recent of 121 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12033708 | Method for programming memory device to reduce retention error | Haibo Li | 2024-07-09 |
| 11935609 | Linked XOR flash data protection scheme | Oleg Kragel, Vijay Sivasankaran, Sahil Sharma | 2024-03-19 |
| 11386970 | Method for programming a memory system | Haibo Li | 2022-07-12 |
| 11334251 | SSD operation in a nonoptimal memory environment | Dmitry Vaysman, Eran Erez, Daniel Tuers, Grishma Shah, Eakta Anchila | 2022-05-17 |
| 11037642 | Method for programming a memory system | Haibo Li | 2021-06-15 |
| 9959915 | Voltage generator to compensate for process corner and temperature variations | Amul Desai, Hao Thai Nguyen, Ohwon Kwon | 2018-05-01 |
| 9947407 | Techniques for programming of select gates in NAND memory | Hao Thai Nguyen, Khanh Nguyen, Seungpil Lee, Toru Ishigaki, Yingda Dong | 2018-04-17 |
| 9947395 | Programming techniques for non-volatile memories with charge trapping layers | Kenneth Louie | 2018-04-17 |
| 9659656 | Techniques for programming of select gates in NAND memory | Hao Thai Nguyen, Khanh Nguyen, Seungpil Lee, Toru Ishigaki, Yingda Dong | 2017-05-23 |
| 9633742 | Segmentation of blocks for faster bit line settling/recovery in non-volatile memory devices | Amul Desai, Hao Thai Nguyen, Seungpil Lee | 2017-04-25 |
| 9627046 | Programming techniques for non-volatile memories with charge trapping layers | Kenneth Louie | 2017-04-18 |
| 9595345 | Adaptive selective bit line pre-charge for current savings and fast programming | Yee Lih Koh, YenLung Li, Cynthia Hsu | 2017-03-14 |
| 9595338 | Utilizing NAND strings in dummy blocks for faster bit line precharge | Juan Lee, Hao Thai Nguyen, Tien-Chien Kuo, Yuki Mizutani | 2017-03-14 |
| 9558836 | Compact high speed sense amplifier for non-volatile memory with reduced layout area and power consumption | Jongmin Park, Hao Thai Nguyen, Seungpil Lee | 2017-01-31 |
| 9552882 | Sense amplifier with efficient use of data latches | Tai-Yuan Tseng, YenLung Li, Cynthia Hsu, Kwang Ho Kim | 2017-01-24 |
| 9502471 | Multi tier three-dimensional memory devices including vertically shared bit lines | Zhenyu Lu, Henry Chien, Johann Alsmeier, Koji Miyata, Tong Zhang +7 more | 2016-11-22 |
| 9466382 | Compensation for sub-block erase | Chris Avila, Yingda Dong | 2016-10-11 |
| 9343156 | Balancing programming speeds of memory cells in a 3D stacked memory | Yongke Sun, Yingda Dong | 2016-05-17 |
| 9330778 | Group word line erase and erase-verify methods for 3D non-volatile memory | Xiying Costa, Alex Mak, Johann Alsmeier | 2016-05-03 |
| 9330779 | Detecting programmed word lines based on NAND string current | Yingda Dong, Chris Avila | 2016-05-03 |
| 9318210 | Word line kick during sensing: trimming and adjacent word lines | James V. Hart, III, Kenneth Louie, Khanh Nguyen | 2016-04-19 |
| 9318204 | Non-volatile memory and method with adjusted timing for individual programming pulses | Han-Ping Chen, Kou Tei | 2016-04-19 |
| 9312026 | Zoned erase verify in three dimensional nonvolatile memory | Mrinal Kochar, Gautam Dusija, Chris Avila, Yingda Dong, Yichao Huang +1 more | 2016-04-12 |
| 9305648 | Techniques for programming of select gates in NAND memory | Hao Thai Nguyen, Khanh Nguyen, Seungpil Lee, Toru Ishigaki, Yingda Dong | 2016-04-05 |
| 9293195 | Compact high speed sense amplifier for non-volatile memory | Jongmin Park, Hao Thai Nguyen, Juan Lee, Seungpil Lee, Alexander Chu | 2016-03-22 |