Issued Patents All Time
Showing 1–25 of 35 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12277347 | Apparatus and methods for back-to-back state machine controller bus operations | Kei Akiyama, Iris Lu, Yoshito Katano | 2025-04-15 |
| 11978516 | Dynamic sense amplifier supply voltage for power and die size reduction | Yanjie Wang, Ohwon Kwon, Kou Tei, Yasue Yamamoto, Yonggang Wu +1 more | 2024-05-07 |
| 11929125 | Window program verify to reduce data latch usage in memory device | Chia-Kai Chou, Iris Lu | 2024-03-12 |
| 11915769 | Non-volatile memory with isolation latch shared between data latch groups | Kei Kitamura, Iris Lu | 2024-02-27 |
| 11901018 | Sense amplifier structure for non-volatile memory with neighbor bit line local data bus data transfer | Iris Lu, Chia-Kai Chou | 2024-02-13 |
| 11875842 | Systems and methods for staggering read operation of sub-blocks | Yu-Chung Lien, Deepanshu Dutta | 2024-01-16 |
| 11798631 | Transfer latch tiers | Iris Lu | 2023-10-24 |
| 11334294 | Microcontroller architecture for non-volatile memory | Chi-Lin Hsu, Yan Li, Hiroyuki Mizukoshi | 2022-05-17 |
| 11301176 | Microcontroller architecture for non-volatile memory | Chi-Lin Hsu, Yan Li, Hiroyuki Mizukoshi | 2022-04-12 |
| 11011242 | Bit line voltage control for damping memory programming | Xiang Yang, Deepanshu Dutta, Gerrit Jan Hemink, Yan Li | 2021-05-18 |
| 10908817 | Signal reduction in a microcontroller architecture for non-volatile memory | Hiroyuki Mizukoshi, Chi-Lin Hsu, Yan Li | 2021-02-02 |
| 10824376 | Microcontroller architecture for non-volatile memory | Chi-Lin Hsu, Yan Li, Hiroyuki Mizukoshi | 2020-11-03 |
| 10748622 | State adaptive predictive programming | Lei Lin, Zhuojie Li, Henry Chin, Gerrit Jan Hemink | 2020-08-18 |
| 10725699 | Microcontroller instruction memory architecture for non-volatile memory | Chi-Lin Hsu, Yan Li, Hiroyuki Mizukoshi | 2020-07-28 |
| 10726921 | Increased terrace configuration for non-volatile memory | Chia-Lin Hsiung, Fumiaki Toyama, Yan Li | 2020-07-28 |
| 10643720 | Bit line voltage control for damping memory programming | Xiang Yang, Deepanshu Dutta, Gerrit Jan Hemink, Yan Li | 2020-05-05 |
| 10510383 | State dependent sense circuits and pre-charge operations for storage devices | Anirudh Amarnath | 2019-12-17 |
| 10366729 | Sense circuit with two-step clock signal for consecutive sensing | Anirudh Amarnath | 2019-07-30 |
| 10366739 | State dependent sense circuits and sense operations for storage devices | Anirudh Amarnath | 2019-07-30 |
| 10255978 | Loop control strobe skew | Kenneth Louie, Qui Vi Nguyen, Jong Hak Yuh, Ohwon Kwon | 2019-04-09 |
| 10121522 | Sense circuit with two sense nodes for cascade sensing | Anirudh Amarnath, Yan Li | 2018-11-06 |
| 10115440 | Word line contact regions for three-dimensional non-volatile memory | Qui Vi Nguyen, Alexander Chu, Kenneth Louie, Anirudh Amarnath, Jixin Yu +2 more | 2018-10-30 |
| 10014063 | Smart skip verify mode for programming a memory device | Huai-Yuan Tseng, Deepanshu Dutta, Grishma Shah, Muhammad Masuduzzaman | 2018-07-03 |
| 9892791 | Fast scan to detect bit line discharge time | Yen-Lung Li, Jong Hak Yuh, Jonathan Huynh, Kwang Ho Kim, Qui Vi Nguyen | 2018-02-13 |
| 9881676 | Sense amplifier with program biasing and fast sensing | Jong Hak Yuh, Raul-Adrian Cernea, Seungpil Lee, Yen-Lung Li, Qui Vi Nguyen +1 more | 2018-01-30 |