Issued Patents All Time
Showing 1–25 of 28 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12333536 | Cryptocurrency using digitally locked coins | DARRION VINH NGUYEN, Hao Vu, Anthony Nguyen | 2025-06-17 |
| 11993456 | Cargo containers having multi-levels and multiple independently opened and closed side doors enabling parallel merchandise loading | — | 2024-05-28 |
| 11685694 | Facile synthesis of solid sodium ion-conductive electrolytes | Younes Ansari, Young-Hye Na, Francisco José Alía Moreno-Ortiz | 2023-06-27 |
| 11600849 | Release layer for preparation of ion-conducting membranes | Robert D. Miller, Young-Hye Na, Sogol Teschler | 2023-03-07 |
| 11264101 | Method of programming in flash memory devices | Yu Wang, Shuang Li, Chunyuan Hou, Qiang Tang | 2022-03-01 |
| 10971708 | Release layer for preparation of ion conducting membranes | Robert D. Miller, Young-Hye Na, Sogol Teschler | 2021-04-06 |
| 10943663 | Method of programming in flash memory devices | Yu Wang, Shuang Li, Chunyuan Hou, Qiang Tang | 2021-03-09 |
| 10614894 | Select gates separation for improving performance in three-dimensional non-volatile memory | Qui Vi Nguyen, Jong Hak Yuh | 2020-04-07 |
| 9947407 | Techniques for programming of select gates in NAND memory | Hao Thai Nguyen, Man Lung Mui, Seungpil Lee, Toru Ishigaki, Yingda Dong | 2018-04-17 |
| 9659656 | Techniques for programming of select gates in NAND memory | Hao Thai Nguyen, Man Lung Mui, Seungpil Lee, Toru Ishigaki, Yingda Dong | 2017-05-23 |
| 9653175 | Determination of word line to word line shorts between adjacent blocks | Jagdish Sabde, Sagar Magia | 2017-05-16 |
| 9514835 | Determination of word line to word line shorts between adjacent blocks | Sagar Magia, Jagdish Sabde | 2016-12-06 |
| 9490020 | Time domain ramp rate control for erase inhibit in flash memory | Kenneth Louie | 2016-11-08 |
| 9449694 | Non-volatile memory with multi-word line select for defect detection operations | Rajan Paudel, Jagdish Sabde, Sagar Magia | 2016-09-20 |
| 9361990 | Time domain ramp rate control for erase inhibit in flash memory | Kenneth Louie | 2016-06-07 |
| 9349458 | Biasing of unselected blocks of non-volatile memory to reduce loading | Kenneth Louie | 2016-05-24 |
| 9349468 | Operational amplifier methods for charging of sense amplifier internal nodes | Kenneth Louie, Hao Thai Nguyen | 2016-05-24 |
| 9318210 | Word line kick during sensing: trimming and adjacent word lines | James V. Hart, III, Kenneth Louie, Man Lung Mui | 2016-04-19 |
| 9305648 | Techniques for programming of select gates in NAND memory | Hao Thai Nguyen, Man Lung Mui, Seungpil Lee, Toru Ishigaki, Yingda Dong | 2016-04-05 |
| 9236128 | Voltage kick to non-selected word line during programming | Kenneth Louie, Man Lung Mui | 2016-01-12 |
| 8107298 | Non-volatile memory with fast binary programming and reduced power consumption | Man Lung Mui, Pao-Ling Koh, Tien-Chien Kuo | 2012-01-31 |
| 7095654 | Method and system for programming and inhibiting multi-level, non-volatile memory cells | Khandker N. Quader, Feng Pan, Long Pham, Alexander Kwok-Tung Mak | 2006-08-22 |
| 6970798 | Method, apparatus and computer program product for high speed memory testing | Tai Anh Cao, Aquilur Rahman | 2005-11-29 |
| 6967872 | Method and system for programming and inhibiting multi-level, non-volatile memory cells | Khandker N. Quader, Feng Pan, Long Pham, Alexander Kwok-Tung Mak | 2005-11-22 |
| 6944068 | Method and system for programming and inhibiting multi-level, non-volatile memory cells | Khandker N. Quader, Feng Pan, Long Pham, Alexander Kwok-Tung Mak | 2005-09-13 |