Issued Patents All Time
Showing 25 most recent of 67 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12046302 | Edge word line concurrent programming with verify for memory apparatus with on-pitch semi-circle drain side select gate technology | Xiang Yang, Deepanshu Dutta | 2024-07-23 |
| 11901007 | Positive TCO voltage to dummy select transistors in 3D memory | Natsu Honda | 2024-02-13 |
| 11894081 | EP cycling dependent asymmetric/symmetric VPASS conversion in non-volatile memory structures | Yu-Chung Lien, Xue Bai Pitner | 2024-02-06 |
| 11688469 | Non-volatile memory with sub-block based self-boosting scheme | Dengtao Zhao, Gerrit Jan Hemink, Xiang Yang, Guirong Liang | 2023-06-27 |
| 11646081 | Reliability compensation for uneven NAND block degradation | Xiang Yang, Peter Rabkin, Henry Chin, Dengtao Zhao, Gerrit Jan Hemink | 2023-05-09 |
| 11625172 | Programming memory cells with concurrent redundant storage of data for power loss protection | Xiang Yang, Toru Miwa, Gerrit Jan Hemink | 2023-04-11 |
| 11551781 | Programming memory cells with concurrent storage of multi-level data as single-level data for power loss protection | Xiang Yang, Toru Miwa, Gerrit Jan Hemink | 2023-01-10 |
| 11545221 | Concurrent programming of multiple cells for non-volatile memory devices | Xiang Yang, Gerrit Jan Hemink, Toru Miwa | 2023-01-03 |
| 11501821 | Three-dimensional memory device containing a shared word line driver across different tiers and methods for making the same | Hiroyuki Ogawa, Mitsuteru Mushiga | 2022-11-15 |
| 11397635 | Block quality classification at testing for non-volatile memory, and multiple bad block flags for product diversity | Shih-Chung Lee, Takashi Murai | 2022-07-26 |
| 11348649 | Threshold voltage setting with boosting read scheme | Kiyohiko Sakakibara, Hiroki Yabe, Masaaki Higashitani | 2022-05-31 |
| 11342028 | Concurrent programming of multiple cells for non-volatile memory devices | Xiang Yang, Aaron Lee, Gerrit Jan Hemink, Toru Miwa | 2022-05-24 |
| 11342029 | Non-volatile memory with switchable erase methods | Huai-Yuan Tseng | 2022-05-24 |
| 11342006 | Buried source line structure for boosting read scheme | Kiyohiko Sakakibara | 2022-05-24 |
| 11322483 | Three-dimensional memory device containing a shared word line driver across different tiers and methods for making the same | Hiroyuki Ogawa, Mitsuteru Mushiga | 2022-05-03 |
| 11227663 | Boosting read scheme with back-gate bias | Kiyohiko Sakakibara, Ippei Yasuda, Masaaki Higashitani | 2022-01-18 |
| 11189335 | Double write/read throughput by CMOS adjacent array (CaA) NAND memory | Masatoshi Nishikawa, Hardwell Chibvongodze | 2021-11-30 |
| 11094715 | Three-dimensional memory device including different height memory stack structures and methods of making the same | Zhixin Cui, Masatoshi Nishikawa | 2021-08-17 |
| 11049580 | Modulation of programming voltage during cycling | Rajdeep Gautam | 2021-06-29 |
| 11024393 | Read operation for non-volatile memory with compensation for adjacent wordline | Zhiping Zhang, Huai-Yuan Tseng, Deepanshu Dutta | 2021-06-01 |
| 11004525 | Modulation of programming voltage during cycling | Rajdeep Gautam | 2021-05-11 |
| 11004518 | Threshold voltage setting with boosting read scheme | Kiyohiko Sakakibara, Hiroki Yabe, Masaaki Higashitani | 2021-05-11 |
| 10978156 | Concurrent programming of multiple cells for non-volatile memory devices | Xiang Yang, Aaron Lee, Gerrit Jan Hemink, Toru Miwa | 2021-04-13 |
| 10978152 | Adaptive VPASS for 3D flash memory with pair string structure | Rajdeep Gautam, Hardwell Chibvongodze | 2021-04-13 |
| 10971231 | Adaptive VPASS for 3D flash memory with pair string structure | Rajdeep Gautam, Hardwell Chibvongodze | 2021-04-06 |