Issued Patents All Time
Showing 26–50 of 67 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10957401 | Boosting read scheme with back-gate bias | Kiyohiko Sakakibara, Ippei Yasuda, Masaaki Higashitani | 2021-03-23 |
| 10950311 | Boosting read scheme with back-gate bias | Kiyohiko Sakakibara, Ippei Yasuda, Masaaki Higashitani | 2021-03-16 |
| 10756106 | Three-dimensional memory device with locally modulated threshold voltages at drain select levels and methods of making the same | Masatoshi Nishikawa, Michiaki Sano, Zhixin Cui | 2020-08-25 |
| 10741579 | Three-dimensional memory device including different height memory stack structures and methods of making the same | Zhixin Cui, Masatoshi Nishikawa | 2020-08-11 |
| 9865352 | Program sequencing | Xiaochang Miao, Genki Sano, Deepanshu Dutta | 2018-01-09 |
| 9548130 | Non-volatile memory with prior state sensing | Deepanshu Dutta, Huai-Yuan Tseng, Dana Lee, Shih-Chung Lee | 2017-01-17 |
| 9543023 | Partial block erase for block programming in non-volatile memory | Chun-Hung Lai, Cheng-Kuan Yin, Shih-Chung Lee, Deepanshu Dutta | 2017-01-10 |
| RE46264 | Verification process for non-volatile storage | Gerrit Jan Hemink, Shih-Chung Lee, Toru Miwa, Yupin Fong, Jun Wan | 2017-01-03 |
| 9324418 | Nonvolatile memory and method for improved programming with reduced verify | Yingda Dong, Cynthia Hsu | 2016-04-26 |
| RE45910 | Programming non-volatile storage including reducing impact from other memory cells | Yingda Dong, Shih-Chung Lee | 2016-03-01 |
| 9214240 | Dynamic erase depth for improved endurance of non-volatile memory | Deepanshu Dutta, Chun-Hung Lai, Shih-Chung Lee, Masaaki Higashitani | 2015-12-15 |
| 9123424 | Optimizing pass voltage and initial program voltage based on performance of non-volatile memory | Shota Murai | 2015-09-01 |
| 9013928 | Dynamic bit line bias for programming non-volatile memory | Deepanshu Dutta, Masaaki Higashitani, Man Lung Mui | 2015-04-21 |
| 8958249 | Partitioned erase and erase verification in non-volatile memory | Deepanshu Dutta, Chun-Hung Lai, Shih-Chung Lee, Masaaki Higashitani | 2015-02-17 |
| 8953386 | Dynamic bit line bias for programming non-volatile memory | Deepanshu Dutta, Masaaki Higashitani, Man Lung Mui | 2015-02-10 |
| 8942047 | Bit line current trip point modulation for reading nonvolatile storage elements | Man Lung Mui, Teruhiko Kamei, Yingda Dong, Yosuke Kato, Fumitoshi Ito +1 more | 2015-01-27 |
| 8929142 | Programming select gate transistors and memory cells using dynamic verify level | Yingda Dong, Cynthia Hsu, Masaaki Higashitani | 2015-01-06 |
| 8913432 | Programming select gate transistors and memory cells using dynamic verify level | Yingda Dong, Cynthia Hsu, Masaaki Higashitani | 2014-12-16 |
| 8908441 | Double verify method in multi-pass programming to suppress read noise | Deepanshu Dutta, Genki Sano, Masaaki Higashitani | 2014-12-09 |
| 8902668 | Double verify method with soft programming to suppress read noise | Deepanshu Dutta, Genki Sano, Masaaki Higashitani | 2014-12-02 |
| 8885416 | Bit line current trip point modulation for reading nonvolatile storage elements | Man Lung Mui, Teruhiko Kamei, Yingda Dong, Yosuke Kato, Fumitoshi Ito +1 more | 2014-11-11 |
| 8885420 | Erase for non-volatile storage | Deepanshu Dutta | 2014-11-11 |
| 8811091 | Non-volatile memory and method with improved first pass programming | Yan Li, Cynthia Hsu | 2014-08-19 |
| 8787088 | Optimized erase operation for non-volatile memory with partially programmed block | Deepanshu Dutta, Koichi Nishimura, Yingda Dong | 2014-07-22 |
| 8755234 | Temperature based compensation during verify operations for non-volatile storage | Yingda Dong, Gerrit Jan Hemink, Man Lung Mui, Hao Thai Nguyen, Seungpil Lee +2 more | 2014-06-17 |