Issued Patents All Time
Showing 1–25 of 41 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12431172 | Operation method for memory device | Chi-Yuan Chin | 2025-09-30 |
| 11817157 | Systems and methods for detecting erratic programming in a memory system | Ming Wang, Liang Li | 2023-11-14 |
| 11797193 | Error detection method for memory device | — | 2023-10-24 |
| 11562797 | Non-linear temperature compensation for wider range operation temperature products | Genki Sano | 2023-01-24 |
| 11397635 | Block quality classification at testing for non-volatile memory, and multiple bad block flags for product diversity | Takashi Murai, Ken Oowada | 2022-07-26 |
| 10373697 | Programming dummy memory cells in erase operation to reduce threshold voltage downshift for select gate transistors | Chun-Hung Lai, Rajdeep Gautam, Ching-Huang Lu | 2019-08-06 |
| 9812281 | X-ray source and X-ray imaging method | Hui-Hsin Lu, Wei Wang, Jiun-Lin Guo | 2017-11-07 |
| 9562363 | Self bonding floor tile | HSIUNG-TIEH YU | 2017-02-07 |
| 9548130 | Non-volatile memory with prior state sensing | Deepanshu Dutta, Huai-Yuan Tseng, Dana Lee, Ken Oowada | 2017-01-17 |
| 9543023 | Partial block erase for block programming in non-volatile memory | Chun-Hung Lai, Cheng-Kuan Yin, Deepanshu Dutta, Ken Oowada | 2017-01-10 |
| RE46264 | Verification process for non-volatile storage | Gerrit Jan Hemink, Toru Miwa, Yupin Fong, Jun Wan, Ken Oowada | 2017-01-03 |
| 9343160 | Erase verify in non-volatile memory | Deepanshu Dutta | 2016-05-17 |
| 9343164 | Compensating source side resistance versus word line | Huai-Yuan Tseng, Dana Lee, Deepanshu Dutta, Arash Hazeghi | 2016-05-17 |
| RE45910 | Programming non-volatile storage including reducing impact from other memory cells | Yingda Dong, Ken Oowada | 2016-03-01 |
| 9236139 | Reduced current program verify in non-volatile memory | Chun-Hung Lai | 2016-01-12 |
| 9214240 | Dynamic erase depth for improved endurance of non-volatile memory | Deepanshu Dutta, Chun-Hung Lai, Ken Oowada, Masaaki Higashitani | 2015-12-15 |
| 8995211 | Program condition dependent bit line charge rate | — | 2015-03-31 |
| 8958249 | Partitioned erase and erase verification in non-volatile memory | Deepanshu Dutta, Chun-Hung Lai, Ken Oowada, Masaaki Higashitani | 2015-02-17 |
| 8942043 | Non-volatile storage with process that reduces read disturb on end wordlines | Jiahui Yuan, Guirong Liang, Wenzhou Chen | 2015-01-27 |
| 8894794 | Method of making a floor panel | Richard H. Balmer, Dung V. Dao, John R. Eshbach, Jr., Heath Harrington, Michael E. Buckwalter +1 more | 2014-11-25 |
| 8804430 | Selected word line dependent select gate diffusion region voltage during programming | Chun-Hung Lai, Shinji Sato, Gerrit Jan Hemink | 2014-08-12 |
| 8720684 | Packaging system for a floor panel | Richard H. Balmer, Dung V. Dao, Christopher R. Knafelc, Heath Harrington, Kean M. Anspach +2 more | 2014-05-13 |
| 8644075 | Ramping pass voltage to enhance channel boost in memory device | Gerrit Jan Hemink, Anubhav Khandelwal, Henry Chin, Guirong Liang, Dana Lee | 2014-02-04 |
| 8526233 | Ramping pass voltage to enhance channel boost in memory device, with optional temperature compensation | Gerrit Jan Hemink, Anubhav Khandelwal, Henry Chin, Guirong Liang, Dana Lee | 2013-09-03 |
| 8472266 | Reducing neighbor read disturb | Anubhav Khandelwal, Jun Wan, Dana Lee | 2013-06-25 |