Issued Patents All Time
Showing 1–25 of 34 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12380960 | Non-volatile memory with faster post-erase defect testing | Sai Gautham Thoppa, Parth Amin | 2025-08-05 |
| 12353275 | Optimized erratic program detection process | Parth Amin, Sai Gautham Thoppa | 2025-07-08 |
| 12334160 | Apparatus and method for detecting neighbor plane erase failures | Parth Amin, Deepanshu Dutta | 2025-06-17 |
| 12272417 | Vera detection method to catch erase fail | Parth Amin, Sai Gautham Thoppa | 2025-04-08 |
| 12087363 | Control gate signal for data retention in nonvolatile memory | Abhijith Prakash | 2024-09-10 |
| 11605430 | Control gate signal for data retention in nonvolatile memory | Abhijith Prakash | 2023-03-14 |
| 11581049 | System and methods for programming nonvolatile memory having partial select gate drains | Kazuki Isozumi, Parth Amin, Sayako Nagamine | 2023-02-14 |
| 11574693 | Memory apparatus and method of operation using periodic normal erase dummy cycle to improve stripe erase endurance and data retention | Chin-Yi Chen, Muhammad Masuduzzaman, Dengtao Zhao, Ravi Kumar | 2023-02-07 |
| 11562798 | Programming techniques for memory devices having partial drain-side select gates | Parth Amin | 2023-01-24 |
| 11545225 | “Read after erase” method for catching single word line “slow to erase” signature in nonvolatile memory structures | Parth Amin | 2023-01-03 |
| 11482289 | Application based verify level offsets for non-volatile memory | Abhijith Prakash | 2022-10-25 |
| 11468950 | Memory programming with selectively skipped bitscans and fewer verify pulses for performance improvement | Abhijith Prakash | 2022-10-11 |
| 11450393 | Countermeasures for periodic over programming for non-volatile memory | Abhijith Prakash | 2022-09-20 |
| 11410739 | Programming techniques with fewer verify pulses to improve performance | Abhijith Prakash | 2022-08-09 |
| 11139030 | Reducing post-read disturb in a nonvolatile memory device | Abhijith Prakash | 2021-10-05 |
| 10878926 | Systems and methods for high-performance write operations | Pitamber Shukla, Mohan Dunga | 2020-12-29 |
| 10790031 | System handling for first read read disturb | Piyush Sagdeo, Chris Yip, Sourabh Sankule, Pitamber Shukla, Mohan Dunga +1 more | 2020-09-29 |
| 10726891 | Reducing post-read disturb in a nonvolatile memory device | Abhijith Prakash, Deepanshu Dutta, Huai-Yuan Tseng, Wei Zhao, Dengtao Zhao | 2020-07-28 |
| 10636504 | Read verify for improved soft bit information for non-volatile memories with residual resistance | Philip Reusswig, Nian Niles Yang | 2020-04-28 |
| 10559366 | Boundary word line voltage shift | Zhenlei Shen, Pitamber Shukla, Philip Reusswig, Niles Yang | 2020-02-11 |
| 10535411 | System and method for string-based erase verify to create partial good blocks | Mohan Dunga, Changyuan Chen, Biswajit Ray | 2020-01-14 |
| 10482986 | Adaptive erase fail bit criteria | Chao-Han Cheng, Nian Niles Yang, Chung-Yao Pai | 2019-11-19 |
| 10460816 | Systems and methods for high-performance write operations | Pitamber Shukla, Mohan Dunga | 2019-10-29 |
| 10204689 | Non-volatile memory with methods to reduce creep-up field between dummy control gate and select gate | Ching-Huang Lu, Changyuan Chen, Cynthia Hsu, Yingda Dong | 2019-02-12 |
| 9978456 | Techniques for reducing read disturb in partially written blocks of non-volatile memory | Dana Lee, Abhijeet Manohar, Henry Chin, Gautam Dusija, Daniel Tuers +2 more | 2018-05-22 |