Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12411608 | I/O modulation scheme for ultra-high data throughput with massive NAND parallelism | Alvin Joshua, Zhixin Cui | 2025-09-09 |
| 12284807 | Three-dimensional memory device with separated contact regions | Hiroyuki Ogawa, Zhixin Cui, Rajdeep Gautam | 2025-04-22 |
| 11889694 | Three-dimensional memory device with separated contact regions and methods for forming the same | Zhixin Cui, Rajdeep Gautam, Hiroyuki Ogawa | 2024-01-30 |
| 11487454 | Systems and methods for defining memory sub-blocks | Masatoshi Nishikawa | 2022-11-01 |
| 11404122 | Sub-block size reduction for 3D non-volatile memory | Masatoshi Nishikawa | 2022-08-02 |
| 11361816 | Memory block with separately driven source regions to improve performance | Zhixin Cui, Rajdeep Gautam | 2022-06-14 |
| 11335671 | Stacked die assembly including double-sided inter-die bonding connections and methods of forming the same | Zhixin Cui, Rajdeep Gautam | 2022-05-17 |
| 11222954 | Three-dimensional memory device containing inter-select-gate electrodes and methods of making the same | Zhixin Cui, Masatoshi Nishikawa | 2022-01-11 |
| 11189335 | Double write/read throughput by CMOS adjacent array (CaA) NAND memory | Masatoshi Nishikawa, Ken Oowada | 2021-11-30 |
| 11081185 | Non-volatile memory array driven from both sides for performance improvement | Masatoshi Nishikawa | 2021-08-03 |
| 11069410 | Three-dimensional NOR-NAND combination memory device and method of making the same | Zhixin Cui, Rajdeep Gautam | 2021-07-20 |
| 11024385 | Parallel memory operations in multi-bonded memory device | Masatoshi Nishikawa | 2021-06-01 |
| 10978152 | Adaptive VPASS for 3D flash memory with pair string structure | Rajdeep Gautam, Ken Oowada | 2021-04-13 |
| 10971231 | Adaptive VPASS for 3D flash memory with pair string structure | Rajdeep Gautam, Ken Oowada | 2021-04-06 |
| 10878907 | Sub-block size reduction for 3D non-volatile memory | Masatoshi Nishikawa | 2020-12-29 |
| 10854619 | Three-dimensional memory device containing bit line switches | Masatoshi Nishikawa, Naoki Ookuma, Takuya Ariki, Toru Miwa | 2020-12-01 |
| 10839918 | Boost converter in memory chip | Masatoshi Nishikawa | 2020-11-17 |
| 10741535 | Bonded assembly containing multiple memory dies sharing peripheral circuitry on a support die and methods for making the same | Masatoshi Nishikawa | 2020-08-11 |
| 10734080 | Three-dimensional memory device containing bit line switches | Masatoshi Nishikawa, Naoki Ookuma, Takuya Ariki, Toru Miwa | 2020-08-04 |
| 10629675 | Three-dimensional memory device containing capacitor pillars and methods of making the same | Masatoshi Nishikawa | 2020-04-21 |
| 10622367 | Three-dimensional memory device including three-dimensional bit line discharge transistors and method of making the same | Masatoshi Nishikawa | 2020-04-14 |
| 7974124 | Pointer based column selection techniques in non-volatile memories | Manabu Sakai, Teruhiko Kamei | 2011-07-05 |