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Word line architecture for three dimensional NAND flash memory |
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Memory plane structure for ultra-low read latency applications in non-volatile memories |
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Word line decoder circuitry under a three-dimensional memory array |
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Differential dbus scheme for low-latency random read for NAND memories |
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Area effective erase voltage isolation in NAND memory |
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Three-dimensional memory device containing bit line switches |
Hardwell Chibvongodze, Masatoshi Nishikawa, Naoki Ookuma, Toru Miwa |
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Three-dimensional memory device containing bit line switches |
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Word line decoder circuitry under a three-dimensional memory array |
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Word line decoder circuitry under a three-dimensional memory array |
Hiroyuki Ogawa, Fumiaki Toyama |
2017-08-01 |
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Integration of word line switches with word line contact via structures |
Hiroyuki Ogawa, Makoto Yoshida, Kazutaka Yoshizawa, Toru Miwa |
2017-03-14 |
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Level shifter with negative voltage capability |
Qui Vi Nguyen, Jongmin Park |
2013-03-12 |
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Flash memory and related voltage regulator |
— |
2011-12-13 |
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Discharge circuit |
— |
2011-02-01 |
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Write voltage generating circuit and method |
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2010-05-04 |
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2004-04-27 |
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— |
2003-03-18 |
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Takeshi Hamamoto, Mikio Asakura, Takayuki Nishiyama |
2002-04-23 |
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Clock synchronous type semiconductor memory device that can switch word configuration |
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Output buffer circuitry for semiconductor integrated circuit device |
— |
2000-04-18 |
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Semiconductor memory device consistently operating a plurality of memory cell arrays distributed in arrangement |
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1999-11-16 |
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Semiconductor memory device with data scramble circuit |
— |
1999-07-20 |
| 5815032 |
Semiconductor device capable of preventing fluctuations of substrate potential |
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1998-09-29 |