Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11177277 | Word line architecture for three dimensional NAND flash memory | Naoki Ookuma, Hiroki Yabe, Koichiro Hayashi, Toru Miwa | 2021-11-16 |
| 11081192 | Memory plane structure for ultra-low read latency applications in non-volatile memories | Hiroki Yabe, Koichiro Hayashi, Yuki Fujita, Naoki Ookuma, Kazuki Yamauchi +2 more | 2021-08-03 |
| 10991429 | Word line decoder circuitry under a three-dimensional memory array | Hiroyuki Ogawa, Fumiaki Toyama | 2021-04-27 |
| 10984874 | Differential dbus scheme for low-latency random read for NAND memories | Hiroki Yabe, Koichiro Hayashi, Naoki Ookuma, Toru Miwa | 2021-04-20 |
| 10885984 | Area effective erase voltage isolation in NAND memory | Hiroki Yabe, Koichiro Hayashi, Yuki Fujita, Naoki Ookuma, Kazuki Yamauchi +2 more | 2021-01-05 |
| 10854619 | Three-dimensional memory device containing bit line switches | Hardwell Chibvongodze, Masatoshi Nishikawa, Naoki Ookuma, Toru Miwa | 2020-12-01 |
| 10734080 | Three-dimensional memory device containing bit line switches | Hardwell Chibvongodze, Masatoshi Nishikawa, Naoki Ookuma, Toru Miwa | 2020-08-04 |
| 10720213 | Word line decoder circuitry under a three-dimensional memory array | Hiroyuki Ogawa, Fumiaki Toyama | 2020-07-21 |
| 9721663 | Word line decoder circuitry under a three-dimensional memory array | Hiroyuki Ogawa, Fumiaki Toyama | 2017-08-01 |
| 9595535 | Integration of word line switches with word line contact via structures | Hiroyuki Ogawa, Makoto Yoshida, Kazutaka Yoshizawa, Toru Miwa | 2017-03-14 |
| 8395434 | Level shifter with negative voltage capability | Qui Vi Nguyen, Jongmin Park | 2013-03-12 |
| 8076911 | Flash memory and related voltage regulator | — | 2011-12-13 |
| 7881122 | Discharge circuit | — | 2011-02-01 |
| 7710793 | Write voltage generating circuit and method | Yuichiro Nakagaki | 2010-05-04 |
| 6727584 | Semiconductor module | Hiroto Tokutome | 2004-04-27 |
| 6535438 | Semiconductor memory device adopting redundancy system | — | 2003-03-18 |
| 6377512 | Clock synchronous type semiconductor memory device that can switch word configuration | Takeshi Hamamoto, Mikio Asakura, Takayuki Nishiyama | 2002-04-23 |
| 6166989 | Clock synchronous type semiconductor memory device that can switch word configuration | Takeshi Hamamoto, Mikio Asakura, Takayuki Nishiyama | 2000-12-26 |
| 6052316 | Output buffer circuitry for semiconductor integrated circuit device | — | 2000-04-18 |
| 5986964 | Semiconductor memory device consistently operating a plurality of memory cell arrays distributed in arrangement | Takeshi Hamamoto, Kiyohiro Furutani | 1999-11-16 |
| 5925141 | Semiconductor memory device with data scramble circuit | — | 1999-07-20 |
| 5815032 | Semiconductor device capable of preventing fluctuations of substrate potential | Hiroshi Akamatsu, Shigeru Mori | 1998-09-29 |