Issued Patents All Time
Showing 1–25 of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12431202 | Memory read calibration based on memory device-originated metrics characterizing voltage distributions | Patrick R. Khayat, Zhengang Chen, Shantilal Rayshi Doru, Hope Henry | 2025-09-30 |
| 12424287 | Memory read voltage threshold tracking based on memory device-originated metrics characterizing voltage distributions | Shantilal Rayshi Doru, Patrick R. Khayat, Steven Michael Kientz, Sampath K. Ratnam | 2025-09-23 |
| 12332743 | Efficient memory use to support soft information in bit flipping decoders | Mustafa N. Kaynak, Eyal En Gad, Zhengang Chen, Sivagnanam Parthasarathy, Phong Sy Nguyen | 2025-06-17 |
| 12334153 | Adaptive pre-read management in multi-pass programming | Kishore Kumar Muchherla, Huai-Yuan Tseng, Akira Goda, Giovanni Maria Paolucci, James Fitzpatrick +3 more | 2025-06-17 |
| 12307090 | Memory device programming technique for increased bits per cell | Tomoharu Tanaka, Huai-Yuan Tseng, Kishore Kumar Muchherla, Eric N. Lee, Akira Goda +2 more | 2025-05-20 |
| 12307121 | Filtering metrics associated with memory | Shantilal Rayshi Doru, Jun Wan, Sampath K. Ratnam | 2025-05-20 |
| 12277978 | Selective and dynamic deployment of error correction code techniques in integrated circuit memory devices | James Fitzpatrick, Phong Sy Nguyen, Sivagnanam Parthasarathy | 2025-04-15 |
| 12266407 | Conditional valley tracking during corrective reads | Tomoharu Tanaka, James Fitzpatrick, Huai-Yuan Tseng, Kishore Kumar Muchherla, Eric N. Lee +2 more | 2025-04-01 |
| 12249364 | Apparatus with non-linear delay variations for scheduling memory refresh operations and methods for operating the same | Huai-Yuan Tseng, Akira Goda, Kishore Kumar Muchherla, James Fitzpatrick, Tomoharu Tanaka +2 more | 2025-03-11 |
| 12131060 | Quick charge loss mitigation using two-pass controlled delay | Kishore Kumar Muchherla, Dave Scott Ebsen, Tomoharu Tanaka, James Fitzpatrick, Huai-Yuan Tseng +2 more | 2024-10-29 |
| 12007838 | Accessing data using error correction operation(s) to reduce latency at a memory sub-system | Vamsi Pavan Rayaprolu, Zixiang Loh, Sampath K. Ratnam, Patrick R. Khayat, Thomas Lentz | 2024-06-11 |
| 11984171 | Selective and dynamic deployment of error correction code techniques in integrated circuit memory devices | James Fitzpatrick, Phong Sy Nguyen, Sivagnanam Parthasarathy | 2024-05-14 |
| 11960722 | Memory device programming technique for increased bits per cell | Tomoharu Tanaka, Huai-Yuan Tseng, Kishore Kumar Muchherla, Eric N. Lee, Akira Goda +2 more | 2024-04-16 |
| 11869595 | Memory device programming technique using fewer latches | Phong Sy Nguyen | 2024-01-09 |
| 11861208 | Performing data operations on grouped memory cells | — | 2024-01-02 |
| 11675655 | Solid-state drive error recovery based on machine learning | Phong Sy Nguyen, Christophe Therene, Nedeljko Varnica | 2023-06-13 |
| 11663079 | Data recovery using a combination of error correction schemes | Phong Sy Nguyen, Sivagnanam Parthasarathy | 2023-05-30 |
| 11568937 | Memory device programming techinique using fewer latches | Phong Sy Nguyen | 2023-01-31 |
| 11562776 | Performing read operations on grouped memory cells | — | 2023-01-24 |
| 11366753 | Controlling performance of a solid state drive | Ka-Ming Keung | 2022-06-21 |
| 11275646 | Solid-state drive error recovery based on machine learning | Phong Sy Nguyen, Christophe Therene, Nedeljko Varnica | 2022-03-15 |
| 10790857 | Systems and methods for using decoders of different complexity in a hybrid decoder architecture | Shashi Kiran Chilappagari, Nedeljko Varnica | 2020-09-29 |
| 10411735 | Systems and methods for an iterative decoding scheme | Shashi Kiran Chilappagari, Phong Sy Nguyen | 2019-09-10 |
| 10084480 | Systems and methods for decoding cascade LDPC codes | Nedeljko Varnica, Shashi Kiran Chilappagari | 2018-09-25 |
| 9755665 | Systems and methods for an iterative decoding scheme | Shashi Kiran Chilappagari, Phong Sy Nguyen | 2017-09-05 |