Issued Patents All Time
Showing 26–50 of 100 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11423993 | Bi-directional sensing in a memory | Zhiping Zhang, Muhammad Masuduzzaman, Peng Zhang, Dengtao Zhao, Deepanshu Dutta | 2022-08-23 |
| 11417400 | Controlling timing and ramp rate of program-inhibit voltage signal during programming to optimize peak current | Yu-Chung Lien, Deepanshu Dutta | 2022-08-16 |
| 11398280 | Lockout mode for reverse order read operation | Yu-Chung Lien, Deepanshu Dutta, Ravi Kumar | 2022-07-26 |
| 11385810 | Dynamic staggering for programming in nonvolatile memory | Yu-Chung Lien, Deepanshu Dutta | 2022-07-12 |
| 11386968 | Memory apparatus and method of operation using plane dependent ramp rate and timing control for program operation | Yu-Chung Lien, Tomer Eliash | 2022-07-12 |
| 11361835 | Countermeasure for reducing peak current during programming by optimizing timing of latch scan operations | Yu-Chung Lien, Fanglin Zhang | 2022-06-14 |
| 11355208 | Triggering next state verify in progam loop for nonvolatile memory | Yu-Chung Lien, Fanglin Zhang, Zhuojie Li | 2022-06-07 |
| 11355198 | Smart erase scheme | Fanqi Wu, Sarath Puthenthermadam | 2022-06-07 |
| 11342029 | Non-volatile memory with switchable erase methods | Ken Oowada | 2022-05-24 |
| 11342033 | Look neighbor ahead for data recovery | Yi Song, Deepanshu Dutta | 2022-05-24 |
| 11335413 | Ramp rate control for peak and average current reduction of open blocks | Yu-Chung Lien, Deepanshu Dutta | 2022-05-17 |
| 11335411 | Erase operation for memory device with staircase word line voltage during erase pulse | Yu-Chung Lien, Keyur Payak | 2022-05-17 |
| 11328754 | Pre-charge timing control for peak current based on data latch count | Yu-Chung Lien, Juan Lee | 2022-05-10 |
| 11315648 | Dynamic tier selection for program verify in nonvolatile memory | Yu-Chung Lien, Dengtao Zhao | 2022-04-26 |
| 11302409 | Programming techniques including an all string verify mode for single-level cells of a memory device | Xue Bai Pitner, Deepanshu Dutta, Ravi Kumar, Cynthia Hsu | 2022-04-12 |
| 11270776 | Countermeasure for reducing peak current during program operation under first read condition | Yu-Chung Lien, Deepanshu Dutta | 2022-03-08 |
| 11250892 | Pre-charge ramp rate control for peak current based on data latch count | Yu-Chung Lien, Juan Lee | 2022-02-15 |
| 11244735 | Systems and methods for program verification on a memory system | Zhiping Zhang, Dengtao Zhao, Deepanshu Dutta | 2022-02-08 |
| 11226772 | Peak power reduction management in non-volatile storage by delaying start times operations | Yu-Chung Lien, Mark Murin, Hua-Ling Cynthia Hsu, Tomer Eliash, Deepanshu Dutta | 2022-01-18 |
| 11211392 | Hole pre-charge scheme using gate induced drain leakage generation | Sarath Puthenthermadam, Yanli Zhang, Peng Zhang | 2021-12-28 |
| 11211127 | Loop dependent plane skew methodology for program operation | Yu-Chung Lien, Hua-Ling Cynthia Hsu | 2021-12-28 |
| 11189351 | Peak and average current reduction for sub block memory operation | Yu-Chung Lien, Sarath Puthenthermadam | 2021-11-30 |
| 11189337 | Multi-stage voltage control for peak and average current reduction of open blocks | Yu-Chung Lien, Deepanshu Dutta | 2021-11-30 |
| 11139038 | Neighboring or logical minus word line dependent verify with sense time in programming of non-volatile memory | Muhammad Masuduzzaman, Deepanshu Dutta | 2021-10-05 |
| 11081162 | Source side precharge and boosting improvement for reverse order program | Sarath Puthenthermadam, Yu-Chung Lien | 2021-08-03 |