Issued Patents All Time
Showing 25 most recent of 37 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12431197 | Programming operation using cache register release in a memory sub-system | Violante Moschiano, Umberto Siciliani | 2025-09-30 |
| 12411770 | Hybrid parallel programming of single-level cell memory | Umberto Siciliani, Violante Moschiano | 2025-09-09 |
| 12393249 | Peak power management with data window reservation | Luca Nubile, Luigi Pilolli | 2025-08-19 |
| 12393526 | NAND page buffer based security operations | Jeremy Binfet, Lance W. Dover, Tommaso Vali | 2025-08-19 |
| 12340851 | Memories for performing successive programming operations | Umberto Siciliani, Violante Moschiano, Dheeraj Srinivasan | 2025-06-24 |
| 12327595 | Shortened single-level cell memory programming | Leo Raimondo, Federica Paolini, Umberto Siciliani, Violante Moschiano, Gianfranco Valeri +1 more | 2025-06-10 |
| 12315574 | Auto-calibrated corrective read | Chengbin Sun, Carmine Miccoli, Violante Moschiano, Srinath Venkatesan | 2025-05-27 |
| 12282669 | Prioritized power budget arbitration for multiple concurrent memory access operations | Luca Nubile, Fumin Gu, Ali Mohammadzadeh, Biagio Iorio, Liang Yu | 2025-04-22 |
| 12205653 | Wordline or pillar state detection for faster read access times | Violante Moschiano, Shyam Sunder Raghunathan | 2025-01-21 |
| 12189949 | Bit error management in memory devices | Jeremy Binfet, Tommaso Vali, Luigi Pilolli, Angelo Covello, Andrea D'Alessandro +3 more | 2025-01-07 |
| 12183407 | Setting switching for single-level cells | Umberto Siciliani, Tao Liu, Ting Luo, Dionisio Minopoli, Giuseppe D'Eliseo +6 more | 2024-12-31 |
| 12165688 | Flash memory devices including dram | Yankang He, Luca Nubile, Chang Hua Siau | 2024-12-10 |
| 12094547 | Continuous memory programming operations | Violante Moschiano, Ali Mohammadzadeh, Dheeraj Srinivasan | 2024-09-17 |
| 12086427 | Power integrity monitoring | Sriteja Yamparala, Fulvio Rori, Marco-Domenico Tiburzi, Chiara Cerafogli, Tawalin Opastrakoon | 2024-09-10 |
| 12087372 | Partial block erase operations in memory devices | Violante Moschiano, Shyam Sunder Raghunathan, Haiou Che | 2024-09-10 |
| 12068034 | Two-pass corrective programming for memory cells that store multiple bits and power loss management for two-pass corrective programming | Kishore Kumar Muchherla, Huai-Yuan Tseng, Giovanni Maria Paolucci, Dave Scott Ebsen, James Fitzpatrick +5 more | 2024-08-20 |
| 12007912 | NAND page buffer based security operations | Jeremy Binfet, Lance W. Dover, Tommaso Vali | 2024-06-11 |
| 12001336 | Hybrid parallel programming of single-level cell memory | Umberto Siciliani, Violante Moschiano | 2024-06-04 |
| 11977748 | Prioritized power budget arbitration for multiple concurrent memory access operations | Luca Nubile, Fumin Gu, Ali Mohammadzadeh, Biagio Iorio, Liang Yu | 2024-05-07 |
| 11908523 | Express programming using advanced cache register release in a memory sub-system | Violante Moschiano, Umberto Siciliani | 2024-02-20 |
| 11842078 | Asynchronous interrupt event handling in multi-plane memory devices | Andrea Giovanni Xotta, Guido Luciano Rizzo, Umberto Siciliani, Tommaso Vali, Luca De Santis | 2023-12-12 |
| 11775185 | Power budget arbitration for multiple concurrent access operations in a memory device | Luca Nubile, Ali Mohammadzadeh, Biagio Iorio, Yuanhang Cao, Luca De Santis +1 more | 2023-10-03 |
| 11636908 | Global-local read calibration | Violante Moschiano, Kishore Kumar Muchherla, Vamsi Pavan Rayaprolu, Jeffrey S. McNeil | 2023-04-25 |
| 11416154 | Partially written block treatment | Sivagnanam Parthasarathy, Terry M. Grunzke, Lucia Botticchio, Vamshi K. Indavarapu, Gianfranco Valeri +4 more | 2022-08-16 |
| 11177014 | Global-local read calibration | Violante Moschiano, Kishore Kumar Muchherla, Vamsi Pavan Rayaprolu, Jeffrey S. McNeil | 2021-11-16 |