Issued Patents All Time
Showing 25 most recent of 39 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12393249 | Peak power management with data window reservation | Luca Nubile, Walter Di Francesco | 2025-08-19 |
| 12277349 | Internal clock signaling | Liang Yu, Biagio Iorio | 2025-04-15 |
| 12248411 | Data burst queue management | Eric N. Lee, Ali Feiz Zarrin Ghalam, Xiangyu Tang, Daniel J. Hubbard | 2025-03-11 |
| 12242400 | Memory device interface communicating with set of data bursts corresponding to memory dies via dedicated portions for command processing | — | 2025-03-04 |
| 12189949 | Bit error management in memory devices | Jeremy Binfet, Tommaso Vali, Walter Di Francesco, Angelo Covello, Andrea D'Alessandro +3 more | 2025-01-07 |
| 12182046 | Data burst suspend mode using pause detection | Eric N. Lee, Leonid Minz, Yoav Weinberg, Ali Feiz Zarrin Ghalam | 2024-12-31 |
| 12111781 | Data burst suspend mode using multi-level signaling | Eric N. Lee, Leonid Minz, Yoav Weinberg, Ali Feiz Zarrin Ghalam | 2024-10-08 |
| 12073918 | Memory device deserializer circuit with a reduced form factor | Guan Wang | 2024-08-27 |
| 11960764 | Memory dice internal clock | Liang Yu, Biagio Iorio | 2024-04-16 |
| 11934325 | Memory device interface communicating with set of data bursts corresponding to memory dies via dedicated portions for command processing | — | 2024-03-19 |
| 11928343 | Peak power management in a memory device | Liang Yu, Jonathan S. Parry | 2024-03-12 |
| 11848071 | Systems and methods involving write training to improve data valid windows | Agatino Massimo Maccarrone, Ali Feiz Zarrin Ghalam, Chin-Yu Chen | 2023-12-19 |
| 11733887 | Write training in memory devices by adjusting delays based on data patterns | Ali Feiz Zarrin Ghalam, Guan Wang, Qiang Tang | 2023-08-22 |
| 11621684 | Memories for receiving or transmitting voltage signals | Agatino Massimo Maccarrone | 2023-04-04 |
| 11594268 | Memory device deserializer circuit with a reduced form factor | Guan Wang | 2023-02-28 |
| 11528015 | Level shifter with reduced duty cycle variation | Ali Feiz Zarrin Ghalam, Myung-Gyoo Won | 2022-12-13 |
| 11520497 | Peak power management in a memory device | Liang Yu, Jonathan S. Parry | 2022-12-06 |
| 11347663 | Memory device interface communicating with set of data bursts corresponding to memory dies via dedicated portions for command processing | — | 2022-05-31 |
| 11282550 | Techniques to calibrate an impedance level | Agatino Massimo Maccarrone, Jiawei Chen, Qiang Tang | 2022-03-22 |
| 11211104 | Systems and methods involving write training to improve data valid windows | Agatino Massimo Maccarrone, Ali Feiz Zarrin Ghalam, Chin-Yu Chen | 2021-12-28 |
| 11079946 | Write training in memory devices | Ali Feiz Zarrin Ghalam, Guan Wang, Qiang Tang | 2021-08-03 |
| 10922220 | Read and program operations in a memory device | Umberto Siciliani, Giulio Marotta, Tommaso Vali, Luca De Santis, Agostino Macerola +3 more | 2021-02-16 |
| 10911033 | Level shifter with reduced duty cycle variation | Ali Feiz Zarrin Ghalam, Myung-Gyoo Won | 2021-02-02 |
| 10861517 | Systems and methods involving memory-side (NAND-side) write training to improve data valid windows | Agatino Massimo Maccarrone, Ali Feiz Zarrin Ghalam, Chin-Yu Chen | 2020-12-08 |
| 10819296 | Apparatus for receiving or transmitting voltage signals | Agatino Massimo Maccarrone | 2020-10-27 |