Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12073918 | Memory device deserializer circuit with a reduced form factor | Luigi Pilolli | 2024-08-27 |
| 12039194 | Unmap backlog in a memory system | Huachen Li, Xu Zhang, Xing Wang, Tian Liang, Junjun Wang | 2024-07-16 |
| 11768782 | Data bus duty cycle distortion compensation | Ali Feiz Zarrin Ghalam, Chin-Yu Chen, Jongin Kim | 2023-09-26 |
| 11740819 | Variable width superblock addressing | Zhao Cui, Eric Kwok Fung Yuen, Xinghui Duan, Hua Chen Li | 2023-08-29 |
| 11733887 | Write training in memory devices by adjusting delays based on data patterns | Luigi Pilolli, Ali Feiz Zarrin Ghalam, Qiang Tang | 2023-08-22 |
| 11594268 | Memory device deserializer circuit with a reduced form factor | Luigi Pilolli | 2023-02-28 |
| 11442877 | Data bus duty cycle distortion compensation | Ali Feiz Zarrin Ghalam, Chin-Yu Chen, Jongin Kim | 2022-09-13 |
| 11341041 | Synchronizing NAND logical-to-physical table region tracking | Zhao Cui, Eric Kwok Fung Yuen, Xinghui Duan, Giuseppe D'Eliseo, Giuseppe Ferrari | 2022-05-24 |
| 11336265 | Internal clock distortion calibration using DC component offset of clock signal | Qiang Tang, Ali Feiz Zarrin Ghalam | 2022-05-17 |
| 11201611 | Duty cycle control circuitry for input/output (I/O) margin control | Qiang Tang, Agatino Massimo Maccarrone | 2021-12-14 |
| 11132136 | Variable width superblock addressing | Zhao Cui, Eric Kwok Fung Yuen, Xinghui Duan, Hua Chen Li | 2021-09-28 |
| 11079946 | Write training in memory devices | Luigi Pilolli, Ali Feiz Zarrin Ghalam, Qiang Tang | 2021-08-03 |
| 10972078 | Internal clock distortion calibration using DC component offset of clock signal | Qiang Tang, Ali Feiz Zarrin Ghalam | 2021-04-06 |
| 10725904 | Synchronizing NAND logical-to-physical table region tracking | Zhao Cui, Eric Kwok Fung Yuen, Xinghui Duan, Giuseppe D'Eliseo, Giuseppe Ferrari | 2020-07-28 |
| 10727816 | Internal clock distortion calibration using dc component offset of clock signal | Qiang Tang, Ali Feiz Zarrin Ghalam | 2020-07-28 |
| 10270429 | Internal clock distortion calibration using DC component offset of clock signal | Qiang Tang, Ali Feiz Zarrin Ghalam | 2019-04-23 |