Issued Patents All Time
Showing 51–75 of 154 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11755478 | Block family combination and voltage bin selection | Michael Sheperek, Larry J. Koudele, Shane Nowell | 2023-09-12 |
| 11748013 | Grouping blocks based on power cycle and power on time | Kishore Kumar Muchherla, Jiangang Wu, Sampath K. Ratnam, Sivagnanam Parthasarathy, Peter Feeley +1 more | 2023-09-05 |
| 11735254 | Error avoidance based on voltage distribution parameters of blocks | Shane Nowell, Steven Michael Kientz, Michael Sheperek, Kishore Kumar Muchherla, Larry J. Koudele +1 more | 2023-08-22 |
| 11727994 | Performing threshold voltage offset bin selection by package for memory devices | Michael Sheperek, Kishore Kumar Muchherla, Vamsi Pavan Rayaprolu, Bruce A. Liikanen, Larry J. Koudele | 2023-08-15 |
| 11722151 | Bit flipping decoder based on soft information | Sivagnanam Parthasarathy | 2023-08-08 |
| 11720286 | Extended cross-temperature handling in a memory sub-system | Vamsi Pavan Rayaprolu, Sampath K. Ratnam, Sivagnanam Parthasarathy, Kishore Kumar Muchherla, Shane Nowell +2 more | 2023-08-08 |
| 11714710 | Providing data of a memory system based on an adjustable error rate | Larry J. Koudele, Michael Sheperek, Patrick R. Khayat, Sampath K. Ratnam | 2023-08-01 |
| 11711095 | Bit flipping low-density parity-check decoders with low error floor | Sivagnanam Parthasarathy | 2023-07-25 |
| 11710527 | Mitigating a voltage condition of a memory cell in a memory sub-system | Vamsi Pavan Rayaprolu, Kishore Kumar Muchherla, Peter Feeley, Sampath K. Ratnam, Sivagnanam Parthasarathy +2 more | 2023-07-25 |
| 11709734 | Error correction with syndrome computation in a memory device | Patrick R. Khayat, Sivagnanam Parthasarathy | 2023-07-25 |
| 11709727 | Managing error-handling flows in memory devices | Kishore Kumar Muchherla, Shane Nowell, Sampath K. Ratnam, Peter Feeley, Sivagnanam Parthasarathy +2 more | 2023-07-25 |
| 11705925 | Dynamic bit flipping order for iterative error correction | Sivagnanam Parthasarathy | 2023-07-18 |
| 11705193 | Error avoidance based on voltage distribution parameters | Shane Nowell, Steven Michael Kientz, Michael Sheperek, Kishore Kumar Muchherla, Larry J. Koudele +1 more | 2023-07-18 |
| 11705192 | Managing read level voltage offsets for low threshold voltage offset bin placements | Kishore Kumar Muchherla, Michael Sheperek, Shane Nowell | 2023-07-18 |
| 11704217 | Charge loss scan operation management in memory devices | Michael Sheperek, Steven Michael Kientz, Shane Nowell, Kishore Kumar Muchherla, Larry J. Koudele | 2023-07-18 |
| 11689217 | Methods and systems of stall mitigation in iterative decoders | Sivagnanam Parthasarathy | 2023-06-27 |
| 11676666 | Read disturb scan for unprogrammed wordlines | Sivagnanam Parthasarathy, Patrick R. Khayat | 2023-06-13 |
| 11676664 | Voltage bin selection for blocks of a memory device after power up of the memory device | Kishore Kumar Muchherla, Sampath K. Ratnam, Shane Nowell, Sivagnanam Parthasarathy, Karl D. Schuh +2 more | 2023-06-13 |
| 11675529 | Threshold voltage determination for calibrating voltage bins of a memory device | Kishore Kumar Muchherla, Sampath K. Ratnam, Shane Nowell, Peter Feeley, Sivagnanam Parthasarathy | 2023-06-13 |
| 11664080 | Bin placement according to program-erase cycles | Michael Sheperek, Steven Michael Kientz | 2023-05-30 |
| 11620074 | Voltage bin calibration based on a voltage distribution reference voltage | Kishore Kumar Muchherla, Devin M. Batutis, Xiangang Luo, Peter Feeley, Sivagnanam Parthasarathy +2 more | 2023-04-04 |
| 11609846 | Managing workload of programming sets of pages to memory device | Kishore Kumar Muchherla, Karl D. Schuh, Jiangang Wu, Devin M. Batutis, Xiangang Luo | 2023-03-21 |
| 11593005 | Managing voltage bin selection for blocks of a memory device | Kishore Kumar Muchherla, Peter Feeley, Sampath K. Ratnam, Shane Nowell, Sivagnanam Parthasarathy +2 more | 2023-02-28 |
| 11587639 | Voltage calibration scans to reduce memory device overhead | Kishore Kumar Muchherla, Sivagnanam Parthasarathy, Xiangang Luo, Peter Feeley, Devin M. Batutis +4 more | 2023-02-21 |
| 11587627 | Determining voltage offsets for memory read operations | Kishore Kumar Muchherla, Sampath K. Ratnam, Shane Nowell, Peter Feeley, Sivagnanam Parthasarathy | 2023-02-21 |