Issued Patents All Time
Showing 76–100 of 154 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11556417 | Reduction of errors in data retrieved from a memory device to apply an error correction code of a predetermined code rate | Sivagnanam Parthasarathy, Kishore Kumar Muchherla, Akira Goda | 2023-01-17 |
| 11532373 | Managing error-handling flows in memory devices | Kishore Kumar Muchherla, Shane Nowell, Sampath K. Ratnam, Peter Feeley, Sivagnanam Parthasarathy +2 more | 2022-12-20 |
| 11514989 | Dynamic adjustment of offset voltages for reading memory cells in a memory device | Sivagnanam Parthasarathy, Patrick R. Khayat | 2022-11-29 |
| 11500564 | Grouping blocks based on power cycle and power on time | Kishore Kumar Muchherla, Jiangang Wu, Sampath K. Ratnam, Sivagnanam Parthasarathy, Peter Feeley +1 more | 2022-11-15 |
| 11463112 | Dynamic bit flipping order for iterative error correction | Sivagnanam Parthasarathy | 2022-10-04 |
| 11462280 | Adjusting pass-through voltage based on threshold voltage shift | Kishore Kumar Muchherla, Sampath K. Ratnam, Peter Feeley, Sivagnanam Parthasarathy | 2022-10-04 |
| 11450391 | Multi-tier threshold voltage offset bin calibration | Kishore Kumar Muchherla, Shane Nowell, Karl D. Schuh, Jiangang Wu, Devin M. Batutis +1 more | 2022-09-20 |
| 11450382 | Memory cell state in a valley between adjacent data states | Sivagnanam Parthasarathy, Patrick R. Khayat, Robert B. Eisenhuth | 2022-09-20 |
| 11443830 | Error avoidance based on voltage distribution parameters of block families | Michael Sheperek, Kishore Kumar Muchherla, Shane Nowell, Larry J. Koudele | 2022-09-13 |
| 11437108 | Voltage bin calibration based on a temporary voltage shift offset | Kishore Kumar Muchherla, Karl D. Schuh, Xiangang Luo, Shane Nowell, Devin M. Batutis +4 more | 2022-09-06 |
| 11429309 | Adjusting a parameter for a programming operation based on the temperature of a memory system | Sampath K. Ratnam, Zixiang Loh, Nagendra Prasad Ganesh Rao, Larry K Koudele, Vamsi Pavan Rayaprolu +2 more | 2022-08-30 |
| 11431355 | Error correction code (ECC) operations in memory for providing redundant error correction | Patrick R. Khayat, Sivagnanam Parthasarathy | 2022-08-30 |
| 11422885 | Tiered error correction code (ECC) operations in memory | Patrick R. Khayat, Sivagnanam Parthasarathy | 2022-08-23 |
| 11410734 | Voltage bin selection for blocks of a memory device after power up of the memory device | Kishore Kumar Muchherla, Sampath K. Ratnam, Shane Nowell, Sivagnanam Parthasarathy, Karl D. Schuh +2 more | 2022-08-09 |
| 11405058 | Stopping criteria for layered iterative error correction | William H. Radke, Patrick R. Khayat, Sivagnanam Parthasarathy | 2022-08-02 |
| 11398835 | Managing defective bitline locations in a bit flipping decoder | Sivagnanam Parthasarathy | 2022-07-26 |
| 11393541 | Mitigating a voltage condition of a memory cell in a memory sub-system | Vamsi Pavan Rayaprolu, Kishore Kumar Muchherla, Peter Feeley, Sampath K. Ratnam, Sivagnanam Parthasarathy +2 more | 2022-07-19 |
| 11394403 | Error correction based on rate adaptive low density parity check (LDPC) codes with flexible column weights in the parity check matrices | Eyal En Gad, Sivagnanam Parthasarathy, Zhengang Chen, Yoav Weinberg | 2022-07-19 |
| 11372545 | Managing bin placement for block families of a memory device based on trigger metric values | Shane Nowell | 2022-06-28 |
| 11360677 | Selective partitioning of sets of pages programmed to memory device | Kishore Kumar Muchherla, Karl D. Schuh, Jiangang Wu, Devin M. Batutis, Xiangang Luo | 2022-06-14 |
| 11349498 | Bit flipping low-density parity-check decoders with low error floor | Sivagnanam Parthasarathy | 2022-05-31 |
| 11334413 | Estimating an error rate associated with memory | Sivagnanam Parthasarathy, Patrick R. Khayat, Nicholas J. Richardson | 2022-05-17 |
| 11275515 | Descrambling of scrambled linear codewords using non-linear scramblers | Patrick R. Khayat, Sivagnanam Parthasarathy | 2022-03-15 |
| 11270772 | Voltage offset bin selection by die group for memory devices | Vamsi Pavan Rayaprolu, Michael Sheperek, Larry J. Koudele, Shane Nowell | 2022-03-08 |
| 11263134 | Block family combination and voltage bin selection | Michael Sheperek, Larry J. Koudele, Shane Nowell | 2022-03-01 |