Issued Patents All Time
Showing 25 most recent of 190 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12211577 | Layout for dual in-line memory to support 128-byte cache line processor | Radoslav Danilak, Rodney N. Mullendore, Chi To | 2025-01-28 |
| 11405058 | Stopping criteria for layered iterative error correction | Mustafa N. Kaynak, Patrick R. Khayat, Sivagnanam Parthasarathy | 2022-08-02 |
| 10998923 | Stopping criteria for layered iterative error correction | Mustafa N. Kaynak, Patrick R. Khayat, Sivagnanam Parthasarathy | 2021-05-04 |
| 10891188 | Memory devices having differently configured blocks of memory cells | Tommaso Vali, Michele Incarnati | 2021-01-12 |
| 10891187 | Memory devices having differently configured blocks of memory cells | Tommaso Vali, Michele Incarnati | 2021-01-12 |
| 10804243 | Dual-sided memory module with channels aligned in opposition | James D. Kelly, Steven J. Sfarzo | 2020-10-13 |
| 10762003 | State change in systems having devices coupled in a chained configuration | Victor Y. Tsai, James Cooke, Neal A. Galbo, Peter Feeley | 2020-09-01 |
| 10664411 | Chained bus memory device | Victor Y. Tsai, Bob Leibowitz | 2020-05-26 |
| 10409673 | Memory devices having differently configured blocks of memory cells | Tommaso Vali, Michele Incarnati | 2019-09-10 |
| 10217721 | Dual-sided memory module with channels aligned in opposition | James D. Kelly, Steven J. Sfarzo | 2019-02-26 |
| 10193577 | Stopping criteria for layered iterative error correction | Mustafa N. Kaynak, Patrick R. Khayat, Sivagnanam Parthasarathy | 2019-01-29 |
| 10089250 | State change in systems having devices coupled in a chained configuration | Victor Y. Tsai, James Cooke, Neal A. Galbo, Peter Feeley | 2018-10-02 |
| 10082957 | Dual-ported PCI express-based storage cartridge including single-ported storage controllers | Pinchas Herman, Vijay Karamcheti, Rodney N. Mullendore | 2018-09-25 |
| 10068655 | Inferring threshold voltage distributions associated with memory cells via interpolation | Zhenlei Shen | 2018-09-04 |
| 9983928 | Apparatuses and methods including error correction code organization | — | 2018-05-29 |
| 9929967 | Packet deconstruction/reconstruction and link-control | Victor Y. Tsai, Peter Feeley, Neal A. Galbo, Robert N. Leibowitz | 2018-03-27 |
| 9901010 | High density server storage unit | Pinchas Herman, Radoslav Danilak | 2018-02-20 |
| 9891675 | Systems and methods for packaging high density SSDs | Pinchas Herman, Radoslav Danilak | 2018-02-13 |
| 9811258 | Methods for controlling host memory access with memory devices and systems | Neal A. Galbo, Peter Feeley, Victor Y. Tsai, Robert N. Leibowitz | 2017-11-07 |
| 9779828 | Inferring threshold voltage distributions associated with memory cells via interpolation | Zhenlei Shen | 2017-10-03 |
| 9766830 | Power consumption control | Krishnam R. Datla, Robin Sarno, Laszlo Borbely-Bartis, Ken Kannampuzha | 2017-09-19 |
| 9702305 | Multiple engine sequencer | Laszlo Borbely, David Christopher Pruett | 2017-07-11 |
| 9654141 | Memory devices and systems configured to adjust a size of an ECC coverage area | — | 2017-05-16 |
| 9646683 | Memory apparatus, systems, and methods | Violante Moschiano, Tommaso Vali, Giovanni Naso, Vishal Sarin, Theodore T. Pekny | 2017-05-09 |
| 9645940 | Apparatus and method for accessing a non-volatile memory blade using multiple controllers in a non-volatile memory based storage device | Radoslav Danilak | 2017-05-09 |