Issued Patents All Time
Showing 25 most recent of 44 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12270573 | Aeolian anti-viral ultra-violet system for fluidic purification | Donald S. Richardson | 2025-04-08 |
| 11560745 | Door closer diagnostics system | Daniel Langenberg, Nathanael L. Thomas, Dakoda Johnson, William J. Jones | 2023-01-24 |
| 11334413 | Estimating an error rate associated with memory | Sivagnanam Parthasarathy, Mustafa N. Kaynak, Patrick R. Khayat | 2022-05-17 |
| 10947764 | Door closer diagnostics system | Daniel Langenberg, Nathanael L. Thomas, Dakoda Johnson, William J. Jones | 2021-03-16 |
| 10846175 | High throughput bit correction of data inside a word buffer for a product code decoder | Sivagnanam Parthasarathy, Patrick R. Khayat, Shantilal Rayshi Doru | 2020-11-24 |
| 10628256 | Updating reliability data | Saeed Sharifi Tehrani | 2020-04-21 |
| 10572338 | Estimating an error rate associated with memory | Sivagnanam Parthasarathy, Mustafa N. Kaynak, Patrick R. Khayat | 2020-02-25 |
| 10498367 | Progressive effort decoder architecture | Sivagnanam Parthasarathy, Patrick R. Khayat, Mustafa N. Kaynak, Ka Leung Ling, Robert B. Eisenhuth | 2019-12-03 |
| 10439648 | Area efficient implementation of a product code error correcting code decoder | Patrick R. Khayat, Sivagnanam Parthasarathy, Shantilal Rayshi Doru | 2019-10-08 |
| 10326479 | Apparatuses and methods for layer-by-layer error correction | Mustafa N. Kaynak, Patrick R. Khayat, Sivagnanam Parthasarathy | 2019-06-18 |
| 10191804 | Updating reliability data | Saeed Sharifi Tehrani | 2019-01-29 |
| 10061643 | Estimating an error rate associated with memory | Sivagnanam Parthasarathy, Mustafa N. Kaynak, Patrick R. Khayat | 2018-08-28 |
| 9654144 | Progressive effort decoder architecture | Sivagnanam Parthasarathy, Patrick R. Khayat, Mustafa N. Kaynak, Ka Leung Ling, Robert B. Eisenhuth | 2017-05-16 |
| 9612903 | Updating reliability data with a variable node and check nodes | Saeed Sharifi Tehrani | 2017-04-04 |
| 9558064 | Estimating an error rate associated with memory | Sivagnanam Parthasarathy, Mustafa N. Kaynak, Patrick R. Khayat | 2017-01-31 |
| 8295286 | Apparatus and method using hashing for efficiently implementing an IP lookup solution in hardware | Suresh Rajgopal, Lun Bin Huang | 2012-10-23 |
| 8055973 | Channel constrained code aware interleaver | Shayan Srinivasa Garani, Xinde Hu, Sivagnanam Parthasarathy | 2011-11-08 |
| 7924839 | Mechanism to reduce lookup latency in a pipelined hardware implementation of a trie-based IP lookup algorithm | Suresh Rajgopal, Lun Bin Huang | 2011-04-12 |
| 7895213 | Method and system for providing cascaded trie-based network packet search engines | — | 2011-02-22 |
| 7782853 | Apparatus and method of using fully configurable memory, multi-stage pipeline logic and an embedded processor to implement multi-bit trie algorithmic network search engine | Lun Bin Huang, Suresh Rajgopal | 2010-08-24 |
| 7715392 | System and method for path compression optimization in a pipelined hardware bitmapped multi-bit trie algorithmic network search engine | Lun Bin Huang, Suresh Rajgopal | 2010-05-11 |
| 7496734 | System and method for handling register dependency in a stack-based pipelined processor | Lun Bin Huang | 2009-02-24 |
| 7299227 | Method and system for providing cascaded trie-based network packet search engines | — | 2007-11-20 |
| 7162481 | Method for increasing storage capacity in a multi-bit trie-based hardware storage engine by compressing the representation of single-length prefixes | Suresh Rajgopal, Lun Bin Huang | 2007-01-09 |
| 7099881 | Method for increasing average storage capacity in a bit-mapped tree-based storage engine by using remappable prefix representations and a run-length encoding scheme that defines multi-length fields to compactly store IP prefixes | Suresh Rajgopal, Lun Bin Huang | 2006-08-29 |