SR

Suresh Rajgopal

Micron: 17 patents #998 of 6,345Top 20%
SS Stmicroelectronics Sa: 6 patents #228 of 1,676Top 15%
IN Intel: 1 patents #18,218 of 30,777Top 60%
Overall (All Time): #169,272 of 4,157,543Top 5%
24
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
12399630 Peak power management priority override Jeremy Binfet, Liang Yu, Jonathan S. Parry, Chulbum Kim, Daniel J. Hubbard 2025-08-26
12399646 Configurable buffered I/O for memory systems Jose Rey C. De Luna, Jeremy W. Butterfield, Dustin J. Carter 2025-08-26
12130755 Serial interface for an active input/output expander of a memory sub-system Chulbum Kim, Dustin J. Carter 2024-10-29
11886358 Ball grid array storage for a memory sub-system Balint Fleischer 2024-01-30
11861207 Management of erase suspend and resume operations in memory devices Chandra M. Guda 2024-01-02
11675696 Active input/output expander of a memory sub-system Jeremy W. Butterfield, Sean E. Nerich, Dustin J. Carter 2023-06-13
11614890 Handling of host-initiated requests in memory sub-systems Marc S. Hamilton 2023-03-28
11455107 Managing sequential write performance consistency for memory devices Ling Wang, Yue Wei, Vamsi Pavan Rayaprolu 2022-09-27
11385949 Apparatus having a multiplexer for passive input/output expansion Dan Soto, Steven Eskildsen 2022-07-12
11347415 Selection component that is configured based on an architecture associated with memory devices Henrico L. Yahja, Steven Eskildsen, Dustin J. Carter 2022-05-31
11301401 Ball grid array storage for a memory sub-system Balint Fleischer 2022-04-12
11237754 Management of erase suspend and resume operations in memory devices Chandra M. Guda 2022-02-01
11182087 Modifying write performance to prolong life of a physical memory device Zhi Kai Feng, Yue Wei 2021-11-23
11132292 Active input/output expander of a memory sub-system Jeremy W. Butterfield, Sean E. Nerich, Dustin J. Carter 2021-09-28
10877678 Selection component that is configured based on an architecture associated with memory devices Henrico L. Yahja, Steven Eskildsen, Dustin J. Carter 2020-12-29
10846158 Apparatus having multiplexers for passive input/output expansion and methods of their operation Dan Soto, Steven Eskildsen 2020-11-24
9411684 Low density parity check circuit Joe Holt, Jacob B. Derouen, Benjamin G. Hess 2016-08-09
8295286 Apparatus and method using hashing for efficiently implementing an IP lookup solution in hardware Lun Bin Huang, Nicholas J. Richardson 2012-10-23
7924839 Mechanism to reduce lookup latency in a pipelined hardware implementation of a trie-based IP lookup algorithm Lun Bin Huang, Nicholas J. Richardson 2011-04-12
7782853 Apparatus and method of using fully configurable memory, multi-stage pipeline logic and an embedded processor to implement multi-bit trie algorithmic network search engine Lun Bin Huang, Nicholas J. Richardson 2010-08-24
7715392 System and method for path compression optimization in a pipelined hardware bitmapped multi-bit trie algorithmic network search engine Lun Bin Huang, Nicholas J. Richardson 2010-05-11
7162481 Method for increasing storage capacity in a multi-bit trie-based hardware storage engine by compressing the representation of single-length prefixes Nicholas J. Richardson, Lun Bin Huang 2007-01-09
7099881 Method for increasing average storage capacity in a bit-mapped tree-based storage engine by using remappable prefix representations and a run-length encoding scheme that defines multi-length fields to compactly store IP prefixes Nicholas J. Richardson, Lun Bin Huang 2006-08-29
6363515 Early power estimation tool for high performance electronic system design Rakesh Patel, Surujeen Singh 2002-03-26