Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Memory devices and systems including static and dynamic caches, and related methods

Memory devices and systems including static and dynamic caches, and related methods

US Patent 12131020 · Granted Oct 29, 2024

Estimated economic value: $30,986,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Trim setting determination on a memory device2025
Program refresh with gate-induced drain leakage2025
Mitigating slow read disturb in a memory sub-system2025
Mitigating slow read disturb in a memory sub-system2025
Buffer allocation for reducing block transit penalty2025
Buffer allocation for reducing block transit penalty2025
Multi-stage erase operation of memory cells in a memory sub-system2025
Multiple-pass programming of memory cells using temporary parity generation2025
Multiple-pass programming of memory cells using temporary parity generation2025
Processing write requests based on queue identifier2025
Temporary parity buffer allocation for zones in a parity group2025
Generating semi-soft bit data during corrective read operations in memory device2025