Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10649906 | Method and system for hardware accelerated row lock for a write back volume | Horia Simionescu, Timothy E. Hoglund, Sridhar Rao Veerla, Gowrisankar Radhakrishnan | 2020-05-12 |
| 10528438 | Method and system for handling bad blocks in a hardware accelerated caching solution | Horia Simionescu, Gowrisankar Radhakrishnan, Timothy E. Hoglund, Sridhar Rao Veerla | 2020-01-07 |
| 10394673 | Method and system for hardware accelerated copyback | Horia Simionescu, Timothy E. Hoglund, Sridhar Rao Veerla, Gowrisankar Radhakrishnan | 2019-08-27 |
| 10282301 | Method and system for hardware accelerated read-ahead caching | Horia Simionescu, Timothy E. Hoglund, Sridhar Rao Veerla, Gowrisankar Radhakrishnan | 2019-05-07 |
| 10282116 | Method and system for hardware accelerated cache flush | Horia Simionescu, Timothy E. Hoglund, Sridhar Rao Veerla, Gowrisankar Radhakrishnan | 2019-05-07 |
| 10223009 | Method and system for efficient cache buffering supporting variable stripe sizes to enable hardware acceleration | Horia Simionescu, Timothy E. Hoglund, Sridhar Rao Veerla, Gowrisankar Radhakrishnan | 2019-03-05 |
| 10108359 | Method and system for efficient cache buffering in a system having parity arms to enable hardware acceleration | Horia Simionescu, Timothy E. Hoglund, Sridhar Rao Veerla, Gowrisankar Radhakrishnan | 2018-10-23 |
| 10078460 | Memory controller utilizing scatter gather list techniques | Horia Simionescu, Timothy E. Hoglund, Sridhar Rao Veerla, Gowrisankar Radhakrishnan | 2018-09-18 |
| 9910798 | Storage controller cache memory operations that forego region locking | Horia Simionescu, Timothy E. Hoglund, Sridhar Rao Veerla, Gowrisankar Radhakrishnan | 2018-03-06 |
| 9910797 | Space efficient formats for scatter gather lists | Horia Simionescu, Timothy E. Hoglund, Sridhar Rao Veerla, Gowrisankar Radhakrishnan | 2018-03-06 |