Issued Patents All Time
Showing 25 most recent of 58 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12354692 | Error detection, correction, and media management on a dram device | Greg S. Hendrix, Anandhavel Nagendrakumar, Krunal Patel, Kirthi Shenoy, Danilo Caraccio +3 more | 2025-07-08 |
| 12347512 | Error detection, correction, and media management on a memory device | Greg S. Hendrix, Anandhavel Nagendrakumar, Krunal Patel, Kirthi Shenoy, Danilo Caraccio +3 more | 2025-07-01 |
| 12340861 | Selective per die DRAM PPR for memory device | Greg S. Hendrix, Anandhavel Nagendrakumar, Krunal Patel, Kirthi Shenoy, Danilo Caraccio +3 more | 2025-06-24 |
| 12217824 | Finite time counting period counting of infinite data streams | Edmund J. Gieske, Cagdas Dirik, Sujeet Ayyapureddi, Yang Lu, Ameen D. Akel +4 more | 2025-02-04 |
| 12182413 | Area-optimized row hammer mitigation | Sujeet Ayyapureddi, Yang Lu, Edmund J. Gieske, Cagdas Dirik, Ameen D. Akel +3 more | 2024-12-31 |
| 12131071 | Row hammer telemetry | Anandhavel Nagendrakumar, Mohammed Ebrahim Hargan, Scott Garner, Danilo Caraccio, Daniele Balluchi +2 more | 2024-10-29 |
| 12119043 | Practical and efficient row hammer error detection | Edmund J. Gieske, Sujeet Ayyapureddi, Yang Lu | 2024-10-15 |
| 12105658 | Intra-chip and inter-chip data protection | Pramod BHARDWAJ, Sarosh I. Azad, Wern-Yan Koe | 2024-10-01 |
| 12067270 | Memory device security and row hammer mitigation | Yang Lu, Sujeet Ayyapureddi, Edmund J. Gieske, Cagdas Dirik, Ameen D. Akel +3 more | 2024-08-20 |
| 12032443 | Shadow DRAM with CRC+RAID architecture, system and method for high RAS feature in a CXL drive | Sandeep Krishna Thirumala, Lingming Yang, Nevil N. Gajera | 2024-07-09 |
| 12019516 | Instant write scheme with delayed parity/raid | Lingming Yang, Sandeep Krishna Thirumala, Nevil N. Gajera | 2024-06-25 |
| 12013756 | Method and memory system for writing data to dram submodules based on the data traffic demand | Lingming Yang, Sandeep Krishna Thirumala, Nevil N. Gajera | 2024-06-18 |
| 11996336 | Electron beam probing techniques and related structures | Radhakrishna Kotti, Mallesh Rajashekharaiah | 2024-05-28 |
| 11961556 | Socket design for a memory device | Radhakrishna Kotti, Rajasekhar Venigalla | 2024-04-16 |
| 11869178 | System for predicting properties of structures, imager system, and related methods | Qianlan Liu, Pradeep Ramachandran, Shawn D. Lyonsmith, Steve K. McCandless, Ted Taylor +2 more | 2024-01-09 |
| 11860228 | Integrated circuit chip testing interface with reduced signal wires | Albert Shih-Huai Lin, Niravkumar Patel, Jane W. Sowards | 2024-01-02 |
| 11782830 | Cache memory with randomized eviction | Sandeep Krishna Thirumala, Lingming Yang, Karthik Sarpatwari, Nevil N. Gajera | 2023-10-10 |
| 11775431 | Cache memory with randomized eviction | Sandeep Krishna Thirumala, Lingming Yang, Karthik Sarpatwari, Nevil N. Gajera | 2023-10-03 |
| 11755804 | Hybrid synchronous and asynchronous control for scan-based testing | Albert Shih-Huai Lin, Rambabu Nerukonda, Niravkumar Patel | 2023-09-12 |
| 11694747 | Self-selecting memory cells configured to store more than one bit per memory cell | Lingming Yang, Xuan Anh Tran, Karthik Sarpatwari, Francesco Douglas Verna-Ketel, Jessica Chen +1 more | 2023-07-04 |
| 11639962 | Scalable scan architecture for multi-circuit block arrays | Niravkumar Patel, Partho Tapan Chaudhuri | 2023-05-02 |
| 11636911 | Leakage source detection for memory with varying conductive path lengths | Radhakrishna Kotti, Patrick Daniel White, Pavan Reddy K. Aella, Rajesh Kamana | 2023-04-25 |
| 11585854 | Runtime measurement of process variations and supply voltage characteristics | Da-Qing Cheng, Nui Chong, Ping-Chin Yeh, Cheang-Whang Chang | 2023-02-21 |
| 11568952 | Adjustable programming pulses for a multi-level cell | Xuan Anh Tran, Nevil N. Gajera, Karthik Sarpatwari | 2023-01-31 |
| 11500017 | Testing memory elements using an internal testing interface | Albert Shih-Huai Lin | 2022-11-15 |