Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12367160 | System and method for valid window maximization in toggle mode link using systematic skew addition to compensate for SSO and crosstalk | Shiv Harit Mathur | 2025-07-22 |
| 11860228 | Integrated circuit chip testing interface with reduced signal wires | Albert Shih-Huai Lin, Amitava Majumdar, Jane W. Sowards | 2024-01-02 |
| 11755804 | Hybrid synchronous and asynchronous control for scan-based testing | Albert Shih-Huai Lin, Rambabu Nerukonda, Amitava Majumdar | 2023-09-12 |
| 11639962 | Scalable scan architecture for multi-circuit block arrays | Amitava Majumdar, Partho Tapan Chaudhuri | 2023-05-02 |
| 11290095 | Programmable dynamic clock stretch for at-speed debugging of integrated circuits | Amitava Majumdar | 2022-03-29 |
| 11263377 | Circuit architecture for expanded design for testability functionality | Amitava Majumdar, Albert Shih-Huai Lin, Partho Tapan Chaudhuri | 2022-03-01 |