Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11860228 | Integrated circuit chip testing interface with reduced signal wires | Albert Shih-Huai Lin, Niravkumar Patel, Amitava Majumdar | 2024-01-02 |
| 9923051 | Substrate noise isolation structures for semiconductor devices | Jing Jing, Shuxian Wu | 2018-03-20 |
| 8224637 | Method and apparatus for modeling transistors in an integrated circuit design | Shuxian Wu, Kaiman Chan | 2012-07-17 |
| 7932563 | Techniques for improving transistor-to-transistor stress uniformity | Jung-Ching J. Ho, Shuxian Wu | 2011-04-26 |
| 7793238 | Method and apparatus for improving a circuit layout using a hierarchical layout description | Peter Rabkin, Zhiyuan Wu, Min-Hsing Chen, Michael J. Hart, Min-Fang Ho | 2010-09-07 |
| 7765498 | Methods of incorporating process-induced layout dimension changes into an integrated circuit simulation netlist | Jonathan Ho, Yan Wang, Xin Wu | 2010-07-27 |
| 7420392 | Programmable gate array and embedded circuitry initialization and processing | David P. Schultz, Stephen M. Douglass, Steven P. Young, Nigel G. Herron, Mehul R. Vashi | 2008-09-02 |
| 6798239 | Programmable gate array having interconnecting logic to support embedded fixed logic circuitry | Stephen M. Douglass, Steven P. Young, Nigel G. Herron, Mehul R. Vashi | 2004-09-28 |
| 6441641 | Programmable logic device with partial battery backup | Raymond C. Pang, Venu M. Kondapalli, Scott O. Frake, Jennifer Wong, F. Erich Goetting +2 more | 2002-08-27 |
| 6366117 | Nonvolatile/battery-backed key in PLD | Raymond C. Pang, Jennifer Wong, Scott O. Frake, Venu M. Kondapalli, F. Erich Goetting +2 more | 2002-04-02 |
| 6218864 | Structure and method for generating a clock enable signal in a PLD | Steven P. Young, Wilson K. Yee | 2001-04-17 |