Issued Patents All Time
Showing 25 most recent of 215 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11750195 | Compute dataflow architecture | Brian C. Gaide | 2023-09-05 |
| 11451230 | Compute dataflow architecture | Brian C. Gaide | 2022-09-20 |
| 11270977 | Power delivery network for active-on-active stacked integrated circuits | Praful Jain, Martin L. Voogel, Brian C. Gaide | 2022-03-08 |
| 11239203 | Multi-chip stacked devices | Brian C. Gaide | 2022-02-01 |
| 10825772 | Redundancy scheme for multi-chip stacked devices | Brian C. Gaide | 2020-11-03 |
| 10715149 | Configurable logic block (CLB) internal routing architecture for enhanced local routing and clocking improvements | Eric F. Dellinger, Jay T. Young, Brian C. Gaide, Chirag Ravishankar, Davis Boyd MOORE | 2020-07-14 |
| 9859896 | Distributed multi-die routing in a multi-chip module | Brian C. Gaide, Eric F. Dellinger | 2018-01-02 |
| 9602108 | Lut cascading circuit | Brian C. Gaide, Alireza S. Kaviani | 2017-03-21 |
| 9509307 | Interconnect multiplexers and methods of reducing contention currents in an interconnect multiplexer | Vikram Santurkar, Anil Kumar Kandala, Santosh Yachareni, Shidong Zhou, Robert Fu +3 more | 2016-11-29 |
| 9438244 | Circuits for and methods of controlling power within an integrated circuit | Santosh Kumar Sood, Brian C. Gaide | 2016-09-06 |
| 9411554 | Signed multiplier circuit utilizing a uniform array of logic blocks | Brian C. Gaide | 2016-08-09 |
| 9177634 | Two gate pitch FPGA memory cell | Yang Hee Song, Nui Chong | 2015-11-03 |
| 9058454 | Method and apparatus to reduce power segmentation overhead within an integrated circuit | James Karp, Michael J. Hart | 2015-06-16 |
| 9002915 | Circuits for shifting bussed data | Brian C. Gaide | 2015-04-07 |
| 8937491 | Clock network architecture | Brian C. Gaide, Trevor J. Bauer, Robert M. Ondris, Dinesh D. Gaitonde | 2015-01-20 |
| 8933447 | Method and apparatus for programmable device testing in stacked die applications | Arifur Rahman, Ramakrishna K. Tanikella, Trevor J. Bauer, Brian C. Gaide | 2015-01-13 |
| 8773166 | Self-timed single track circuit | Brian C. Gaide | 2014-07-08 |
| 8773164 | Programmable interconnect network | Brian C. Gaide | 2014-07-08 |
| 8768570 | Wheel cover system for a 3-wheeled motorcycle | — | 2014-07-01 |
| 8706793 | Multiplier circuits with optional shift function | — | 2014-04-22 |
| 8543291 | Hydraulic wheel suspension system for a 3-wheeled motorcycle | — | 2013-09-24 |
| 8536895 | Configuration of a multi-die integrated circuit | Weiguang Lu, Eric E. Edwards, Paul-Hugo Lamarche, Brian C. Gaide, Joe Eddie Leyba, II | 2013-09-17 |
| 8527572 | Multiplier architecture utilizing a uniform array of logic blocks, and methods of using the same | Brian C. Gaide | 2013-09-03 |
| 8495122 | Programmable device with dynamic DSP architecture | James M. Simkins, Jennifer Wong, Bernard J. New, Alvin Y. Ching | 2013-07-23 |
| 8301988 | Error checking parity and syndrome of a block of data with relocated parity bits | Warren E. Cory, David P. Schultz | 2012-10-30 |