Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10998904 | Programmable termination circuits for programmable devices | Sundeep Ram Gopal Agarwal, Brian C. Gaide | 2021-05-04 |
| 10804255 | Circuit for and method of transmitting a signal in an integrated circuit device | Sundeep Ram Gopal Agarwal | 2020-10-13 |
| 10503861 | Placing and routing an interface portion and a main portion of a circuit design | Dinesh D. Gaitonde, Henri Fraisse, Sachin K. Bhutada, Aashish TRIPATHI | 2019-12-10 |
| 9054684 | Single event upset enhanced architecture | Santosh Kumar Sood, Praful Jain | 2015-06-09 |
| 9000529 | Reduction of single event upsets within a semiconductor integrated circuit | Praful Jain, James Karp, Michael J. Hart | 2015-04-07 |
| 8933447 | Method and apparatus for programmable device testing in stacked die applications | Arifur Rahman, Trevor J. Bauer, Brian C. Gaide, Steven P. Young | 2015-01-13 |
| 8120382 | Programmable integrated circuit with mirrored interconnect structure | Trevor J. Bauer, Steven P. Young | 2012-02-21 |
| 8001511 | Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC dies | Trevor J. Bauer, Jeffrey V. Lindholm, F. Erich Goetting, Bruce E. Talley, Steven P. Young | 2011-08-16 |
| 7743175 | Methods of initializing routing structures in integrated circuits | Steven P. Young | 2010-06-22 |
| 7548089 | Structures and methods to avoiding hold time violations in a programmable logic device | Trevor J. Bauer, Steven P. Young | 2009-06-16 |
| 7451421 | Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC dies | Trevor J. Bauer, Jeffrey V. Lindholm, F. Erich Goetting, Bruce E. Talley, Steven P. Young | 2008-11-11 |
| 7382157 | Interconnect driver circuits for dynamic logic | Steven P. Young, Manoj Chirania, Venu M. Kondapalli | 2008-06-03 |
| 7312631 | Structures and methods for avoiding hold time violations in a programmable logic device | Trevor J. Bauer, Steven P. Young | 2007-12-25 |
| 7199610 | Integrated circuit interconnect structure having reduced coupling between interconnect lines | Steven P. Young, Sanjiv Stokes | 2007-04-03 |
| 7075332 | Six-input look-up table and associated memory control circuitry for use in a field programmable gate array | Steven P. Young, Venu M. Kondapalli | 2006-07-11 |
| 7061271 | Six-input look-up table for use in a field programmable gate array | Steven P. Young, Venu M. Kondapalli | 2006-06-13 |
| 6933747 | Structures and methods of testing interconnect structures in programmable logic devices | Trevor J. Bauer, Steven P. Young | 2005-08-23 |